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drm/amdgpu: change gfx9 ib test to use WB

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two reasons to switch SCRATCH reg method to WB method:

1)Because when doing IB test we don't want to involve KIQ health
status affect, and since SCRATCH register access is go through
KIQ that way GFX IB test would failed due to KIQ fail.

2)acccessing SCRATCH register cost much more time than WB method
because SCRATCH register access runs through KIQ which at least could
begin after GPU world switch back to current Guest VF

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Monk Liu 2018-01-23 18:29:22 +08:00 • committed by Alex Deucher
parent 113890ee99
commit ed9324afc0
1 changed files with 54 additions and 47 deletions
Download patch file Download diff file Expand all files Collapse all files

35
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
View file

@ -274,26 +274,32 @@ static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
struct amdgpu_device *adev = ring->adev; struct amdgpu_device *adev = ring->adev;
struct amdgpu_ib ib; struct amdgpu_ib ib;
struct dma_fence *f = NULL; struct dma_fence *f = NULL;
uint32_t scratch;
uint32_t tmp = 0; unsigned index;
uint64_t gpu_addr;
uint32_t tmp;
long r; long r;
r = amdgpu_gfx_scratch_get(adev, &scratch); r = amdgpu_device_wb_get(adev, &index);
if (r) { if (r) {
DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r); dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
return r; return r;
} }
WREG32(scratch, 0xCAFEDEAD);
gpu_addr = adev->wb.gpu_addr + (index * 4);
adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
memset(&ib, 0, sizeof(ib)); memset(&ib, 0, sizeof(ib));
r = amdgpu_ib_get(adev, NULL, 256, &ib); r = amdgpu_ib_get(adev, NULL, 16, &ib);
if (r) { if (r) {
DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r); DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
goto err1; goto err1;
} }
ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1); ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START)); ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
ib.ptr[2] = 0xDEADBEEF; ib.ptr[2] = lower_32_bits(gpu_addr);
ib.length_dw = 3; ib.ptr[3] = upper_32_bits(gpu_addr);
ib.ptr[4] = 0xDEADBEEF;
ib.length_dw = 5;
r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f); r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
if (r) if (r)
@ -308,20 +314,21 @@ static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r); DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
goto err2; goto err2;
} }
tmp = RREG32(scratch);
tmp = adev->wb.wb[index];
if (tmp == 0xDEADBEEF) { if (tmp == 0xDEADBEEF) {
DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx); DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
r = 0; r = 0;
} else { } else {
DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n", DRM_ERROR("ib test on ring %d failed\n", ring->idx);
scratch, tmp);
r = -EINVAL; r = -EINVAL;
} }
err2: err2:
amdgpu_ib_free(adev, &ib, NULL); amdgpu_ib_free(adev, &ib, NULL);
dma_fence_put(f); dma_fence_put(f);
err1: err1:
amdgpu_gfx_scratch_free(adev, scratch); amdgpu_device_wb_free(adev, index);
return r; return r;
} }