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dt-bindings: display/msm: split qcom, mdss bindings
Split Mobile Display SubSystem (MDSS) root node bindings to the separate yaml file. Changes to the existing (txt) schema: - Added optional "vbif_nrt_phys" region used by msm8996 - Made "bus" and "vsync" clocks optional (they are not used by some platforms) - Added optional resets property referencing MDSS reset - Defined child nodes pointing to corresponding reference schema. - Dropped the "lut" clock. It was added to the schema by mistake (it is a part of mdp4 schema, not the mdss). Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/508378/ Link: https://lore.kernel.org/r/20221024164225.3236654-2-dmitry.baryshkov@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Dmitry Baryshkov
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2 changed files with 197 additions and 29 deletions
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@ -2,37 +2,9 @@ Qualcomm adreno/snapdragon MDP5 display controller
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Description:
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This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
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encapsulates sub-blocks like MDP5, DSI, HDMI, eDP etc, and the MDP5 display
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This is the bindings documentation for the MDP5 display
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controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 and MSM8996.
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MDSS:
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Required properties:
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- compatible:
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* "qcom,mdss" - MDSS
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- reg: Physical base address and length of the controller's registers.
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- reg-names: The names of register regions. The following regions are required:
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* "mdss_phys"
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* "vbif_phys"
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- interrupts: The interrupt signal from MDSS.
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- interrupt-controller: identifies the node as an interrupt controller.
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- #interrupt-cells: specifies the number of cells needed to encode an interrupt
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source, should be 1.
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- power-domains: a power domain consumer specifier according to
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Documentation/devicetree/bindings/power/power_domain.txt
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- clocks: device clocks. See ../clocks/clock-bindings.txt for details.
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- clock-names: the following clocks are required.
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* "iface"
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* "bus"
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* "vsync"
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- #address-cells: number of address cells for the MDSS children. Should be 1.
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- #size-cells: Should be 1.
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- ranges: parent bus address space is the same as the child bus address space.
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Optional properties:
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- clock-names: the following clocks are optional:
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* "lut"
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MDP5:
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Required properties:
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- compatible:
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196
Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
Normal file
196
Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml
Normal file
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@ -0,0 +1,196 @@
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# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,mdss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Mobile Display SubSystem (MDSS)
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maintainers:
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- Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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- Rob Clark <robdclark@gmail.com>
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description:
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This is the bindings documentation for the Mobile Display Subsytem(MDSS) that
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encapsulates sub-blocks like MDP5, DSI, HDMI, eDP, etc.
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properties:
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compatible:
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enum:
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- qcom,mdss
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reg:
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minItems: 2
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maxItems: 3
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reg-names:
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minItems: 2
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items:
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- const: mdss_phys
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- const: vbif_phys
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- const: vbif_nrt_phys
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interrupts:
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maxItems: 1
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interrupt-controller: true
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"#interrupt-cells":
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const: 1
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power-domains:
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maxItems: 1
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description: |
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The MDSS power domain provided by GCC
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clocks:
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minItems: 1
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items:
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- description: Display abh clock
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- description: Display axi clock
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- description: Display vsync clock
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clock-names:
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minItems: 1
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items:
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- const: iface
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- const: bus
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- const: vsync
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"#address-cells":
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const: 1
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"#size-cells":
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const: 1
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ranges: true
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resets:
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items:
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- description: MDSS_CORE reset
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-controller
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- "#interrupt-cells"
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- power-domains
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- clocks
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- clock-names
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- "#address-cells"
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- "#size-cells"
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- ranges
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patternProperties:
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"^mdp@[1-9a-f][0-9a-f]*$":
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type: object
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properties:
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compatible:
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const: qcom,mdp5
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"^dsi@[1-9a-f][0-9a-f]*$":
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type: object
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properties:
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compatible:
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const: qcom,mdss-dsi-ctrl
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"^phy@[1-9a-f][0-9a-f]*$":
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type: object
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properties:
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compatible:
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enum:
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- qcom,dsi-phy-14nm
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- qcom,dsi-phy-14nm-660
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- qcom,dsi-phy-14nm-8953
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- qcom,dsi-phy-20nm
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- qcom,dsi-phy-28nm-hpm
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- qcom,dsi-phy-28nm-lp
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"^hdmi-phy@[1-9a-f][0-9a-f]*$":
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type: object
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properties:
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compatible:
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enum:
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- qcom,hdmi-phy-8084
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- qcom,hdmi-phy-8660
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- qcom,hdmi-phy-8960
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- qcom,hdmi-phy-8974
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- qcom,hdmi-phy-8996
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"^hdmi-tx@[1-9a-f][0-9a-f]*$":
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type: object
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properties:
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compatible:
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enum:
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- qcom,hdmi-tx-8084
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- qcom,hdmi-tx-8660
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- qcom,hdmi-tx-8960
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- qcom,hdmi-tx-8974
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- qcom,hdmi-tx-8994
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- qcom,hdmi-tx-8996
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-msm8916.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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mdss@1a00000 {
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compatible = "qcom,mdss";
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reg = <0x1a00000 0x1000>,
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<0x1ac8000 0x3000>;
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reg-names = "mdss_phys", "vbif_phys";
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power-domains = <&gcc MDSS_GDSC>;
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clocks = <&gcc GCC_MDSS_AHB_CLK>,
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<&gcc GCC_MDSS_AXI_CLK>,
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<&gcc GCC_MDSS_VSYNC_CLK>;
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clock-names = "iface",
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"bus",
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"vsync";
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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mdp@1a01000 {
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compatible = "qcom,mdp5";
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reg = <0x01a01000 0x89000>;
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reg-names = "mdp_phys";
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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clocks = <&gcc GCC_MDSS_AHB_CLK>,
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<&gcc GCC_MDSS_AXI_CLK>,
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<&gcc GCC_MDSS_MDP_CLK>,
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<&gcc GCC_MDSS_VSYNC_CLK>;
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clock-names = "iface",
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"bus",
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"core",
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"vsync";
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iommus = <&apps_iommu 4>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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mdp5_intf1_out: endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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};
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};
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};
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...
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