Commit graph

8680 commits

Author SHA1 Message Date
James Zhu
368d0dd81a drm/amdgpu/vcn:Add DPG mode Register XX check
Add Dynamic Power Gate mode Register XX check

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:54:47 -05:00
James Zhu
abd2d47c51 drm/amdgpu/vcn:Update DPG mode VCN global tiling registers
Update Dynamic Power Gate mode VCN global tiling registers

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:54:40 -05:00
James Zhu
6747c2021c drm/amdgpu/vcn:Update DPG mode VCN memory control
Update Dynamic Power Gate mode VCN memory control

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:54:33 -05:00
James Zhu
cce9d55585 drm/amdgpu/vcn:Reduce unnecessary local variable
Reduce unnecessary local variable.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:54:25 -05:00
James Zhu
15296db706 drm/amdgpu/vcn:Add ring W/R PTR check for VCN DPG mode stop
Add ring write/read pointer check for VCN dynamic power gate mode
stop,to make sure that no job is left in ring before turn off DPG mode.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:54:17 -05:00
James Zhu
5866fb929c drm/amdgpu/vcn:Update latest spg mode stop for VCN
Update latest static power gate mode stop function for VCN

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:54:09 -05:00
James Zhu
5327f025dc drm/amdgpu/vcn:Update latest UVD_MPC register for VCN
Update latest UVD_MPC register for VCN. Use defined
macro to replace value for readability.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:54:02 -05:00
James Zhu
b53d3049d2 drm/amdgpu/vcn:Add new register offset/mask for VCN
Add new register offset/mask for VCN to support
latest VCN implementation.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:53:52 -05:00
hersen wu
8c6259beda drm/amdgpu/display: dm/amdgpu: make dp phy debugfs for eDP
[WHY] dp debugfs file does not exist for eDP under
      /sys/kernel/debug/dri/0/eDP-1. the root is phy debugfs
      is created for dp connector only.
[HOW] for eDP connector, create phy debugfs too.

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: David Francis <David.Francis@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:53:04 -05:00
Emily Deng
8bda1013dd drm/amdgpu: Set the default value about gds vmid0 size
For sriov, when first run windows guest, then run linux guest, the gds
vmid0 size will be reset to 0 by windows guest. So if the value has been
reset to 0, then set the value to the default value in linux guest.

v2:
Fixed value instead of reading mmGDS_VMID0_SIZE.

v3:
Set the default value of the switch.

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:52:49 -05:00
Evan Quan
7a862028b9 drm/amd/powerplay: hint when power profile setting is not supported
Give user some hints when the power profile setting is not supported.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:22:16 -05:00
Evan Quan
73d0a44669 drm/amd/powerplay: translate power_profile mode to pplib workload type
Correctly translate the power profile specified by user to workload
type accepted by SMU fw.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-12 12:22:16 -05:00
Alex Deucher
a553c19d15 drm/amdgpu/powerplay: factor out some pptable helpers
Move copy_array helpers to smu_helper.c and share between
vega12 and vega20.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:44 -05:00
Alex Deucher
99e219521d drm/amdgpu/powerplay: endian fixes for vega20_processpptables.c
Properly swap data from vbios.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:44 -05:00
Alex Deucher
d97a7ab394 drm/amdgpu/powerplay: endian fixes for vega12_processpptables.c
Properly swap data from vbios.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:43 -05:00
Alex Deucher
de50176330 drm/amdgpu/powerplay: endian fixes for vega10_processpptables.c
Properly swap data from vbios.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:43 -05:00
YueHaibing
f667dc38aa drm/amdgpu: remove set but not used variable 'header'
Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c: In function 'amdgpu_ucode_init_bo':
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c:431:39: warning:
 variable 'header' set but not used [-Wunused-but-set-variable]

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:43 -05:00
YueHaibing
50325c0be1 drm/amdgpu: remove set but not used variable 'ring' in psp_v11_0_ring_stop
Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/amdgpu/psp_v11_0.c: In function 'psp_v11_0_ring_stop':
drivers/gpu/drm/amd/amdgpu/psp_v11_0.c:309:19: warning:
 variable 'ring' set but not used [-Wunused-but-set-variable]

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:42 -05:00
YueHaibing
ae5c59a83b drm/amdkfd: Remove set but not used variable 'preempt_all_queues'
Fixes gcc '-Wunused-but-set-variable' warning:

drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c: In function 'destroy_queue_cpsch':
drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c:1366:7: warning:
 variable 'preempt_all_queues' set but not used [-Wunused-but-set-variable]

It never used since introduct in
commit 992839ad64 ("drm/amdkfd: Add static user-mode queues support")

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:42 -05:00
Colin Ian King
14b284832e drm/amdgpu/powerplay: fix missing break in switch statements
There are several switch statements that are missing break statements.
Add missing breaks to handle any fall-throughs corner cases.

Detected by CoverityScan, CID#1457175 ("Missing break in switch")

Fixes: 18aafc59b1 ("drm/amd/powerplay: implement fw related smu interface for iceland.")
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:41 -05:00
Lyude Paul
582f58de36 drm/amdgpu: Suppress keypresses from ACPI_VIDEO events
Currently we return NOTIFY_DONE for any event which we don't think is
ours. However, many laptops will send more then just an ATIF event and
will also send an ACPI_VIDEO_NOTIFY_PROBE event as well. Since we don't
check for this, we return NOTIFY_DONE which causes a keypress for the
ACPI event to be propogated to userspace. This is the equivalent of
someone pressing the display key on a laptop every time there's a
hotplug event.

So, check for ACPI_VIDEO_NOTIFY_PROBE events and suppress keypresses
from them.

Signed-off-by: Lyude Paul <lyude@redhat.com>
Cc: stable@vger.kernel.org
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:41 -05:00
Rex Zhu
8005164806 drm/amdgpu: Remove the direct fw loading support for sdma2.4
sdma2.4 is only for iceland. For Vi, we don't maintain the
direct fw loading.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:34 -05:00
Rex Zhu
b19caa17b5 drm/amdgpu: Remove wrong fw loading type warning
Remove the warning message:
"-1 is not supported on VI"
the -1 is the default fw load type, mean auto.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:27 -05:00
Rex Zhu
7a3e0bb2a5 drm/amdgpu: Load fw between hw_init/resume_phase1 and phase2
Extract the function of fw loading out of powerplay.
Do fw loading between hw_init/resuem_phase1 and phase2

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:21 -05:00
Rex Zhu
0a4f25205e drm/amdgpu: split ip hw_init into 2 phases
We need to do some IPs earlier to deal with ordering issues
similar to how resume is split into two phases.

Will do fw loading via smu/psp between the two phases.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:09 -05:00
Rex Zhu
735f654e5d drm/amdgpu: Remove amdgpu_ucode_fini_bo
The variable clean is unnecessary.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:49:01 -05:00
Rex Zhu
c8963ea4ce drm/amdgpu: Split amdgpu_ucode_init/fini_bo into two functions
1. one is for create/free bo when init/fini
2. one is for fill the bo before fw loading

the ucode bo only need to be created when load driver
and free when driver unload.

when resume/reset, driver only need to re-fill the bo
if the bo is allocated in vram.

Suggested by Christian.

v2: Return error when bo create failed.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:48:52 -05:00
Rex Zhu
a2d31dc3cf drm/amdgpu: Check late_init status before set cg/pg state
Fix cg/pg unexpected set in hw init failed case.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:48:44 -05:00
Rex Zhu
73f847dbab drm/amdgpu: Refine function amdgpu_device_ip_late_init
1. only call late_init when hw_init successful,
   so check status.hw instand of status.valid in late_init.
2. set status.late_initialized true if late_init was not implemented.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:48:28 -05:00
Rex Zhu
009d9ed6c4 drm/amdgpu: Change AI gfx/sdma/smu init sequence
initialize gfx/sdma before dpm features enabled.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:48:18 -05:00
Rex Zhu
3089aa2248 drm/amdgpu: Change SI/CI gfx/sdma/smu init sequence
initialize gfx/sdma before dpm features enabled.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:48:11 -05:00
Emily Deng
f2d9bbc996 drm/amdgpu: Limit the max mc address to hole start
For the vram_start is 0 case, the gart range will be from 0x0000FFFF00000000
to 0x0000FFFF1FFFFFFF, which will cause the engine hang.

So to avoid the hole, limit the max mc address to AMDGPU_GMC_HOLE_START.:wq

Signed-off-by: Emily Deng <Emily.Deng@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:48:02 -05:00
Tao Zhou
f9f97e3c7f drm/amdgpu: fix CPDMA hang in PRT mode
Fix CPDMA hang in PRT mode, set CPF_INT_DMA in reg CP_MECx_F32_INT_DIS for Compute and set DISABLE_GFX_HALT_ON_UTCL1_ERROR in reg CP_DEBUG for GFX

Affected ASICs: Vega10 Vega12 Raven

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Tested-by: Yukun.Li <yukun1.li@amd.com>
Tested-by: Maciej.Jesionowski <maciej.jesionowski@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:47:39 -05:00
Tao Zhou
04e7580f89 drm/amdgpu: add CP_DEBUG register definition for GC9.0
Add CP_DEBUG register definition.

Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:47:32 -05:00
Hersen Wu
66f34aeec2 drm/amd/display: RV2 DP MST 2nd display within daisy chain not light up
RV2 resource is limit to 3 pipes. Limitation should apply to all HW
blocks instead of front pipe.

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:47:24 -05:00
Roman Li
d567cc55c0 drm/amd/display: Fix warning storm on Raven2
[Why]
Wrong index for pstate debug test register

[How]
Add correct index value for dcn1_01 in hubbub1_construct()

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-10 14:47:04 -05:00
Rex Zhu
71195ba670 drm/amdgpu: Change VI gfx/sdma/smu init sequence
initialize gfx/sdma before dpm features enabled.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:08:25 -05:00
Rex Zhu
9d5aa2ef38 drm/amdgpu: Add fw load in gfx_v8 and sdma_v3
gfx and sdma can be initialized before smu.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:08:17 -05:00
Rex Zhu
9c8bc8d339 drm/amd/pp: Implement load_firmware interface
with this interface, gfx/sdma can be initialized
before smu.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:08:10 -05:00
Rex Zhu
744a522794 drm/amd/pp: Allocate ucode bo in request_smu_load_fw
ucode bo is needed by request_smu_load_fw,
the request_smu_load_fw maybe called by gfx/sdma
before smu hw init.
so move amdgpu_ucode_bo_init to request_smu_lowd_fw
from smu hw init.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:08:04 -05:00
Rex Zhu
07da6aa47f drm/amdgpu: Don't reallocate ucode bo when suspend
driver don't release the ucode memory when suspend. so don't
need to allocate bo when resume back.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:07:57 -05:00
Rex Zhu
9b008fb7ed drm/amdgpu: Remove FW_LOAD_DIRECT type support on VI
AMDGPU_FW_LOAD_DIRECT is used for bring up.
Now it don't work any more. so remove the support.

v2: Add warning message if user select
   AMDGPU_FW_LOAD_DIRECT/AMDGPU_FW_LOAD_PSP on VI.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:07:49 -05:00
James Zhu
825da4d925 drm/amdgpu/vcn:Correct VCN cache window definition
Correct VCN cache window definition. The old one
is reused from UVD, and it is not fully correct.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:07:39 -05:00
James Zhu
b17c524922 drm/amdgpu/vcn:Replace value with defined macro
Replace value with defined macro to make
code more readable

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:07:33 -05:00
James Zhu
2dc4aa523b drm/amdgpu/vcn:fix dpg pause mode hang issue
Use mmUVD_SCRATCH2 tracking decode write point.
It will help avoid dpg pause mode hang issue.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:07:26 -05:00
James Zhu
9332ddc915 drm/amdgpu/vcn:Remove unused code
The following WREG32_SOC15_DPG_MODE will overwrite register
mmUVD_CGC_CTRL. This code can be removed.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:07:19 -05:00
Christian König
4eb10b5be7 drm/amdgpu: fix incorrect use of amdgpu_irq_add_id in si_dma.c
Adding a second irq source because of a different src_id is actually a
bug.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:07:05 -05:00
Christian König
2ccecaf661 drm/amdgpu: fix AGP location with VRAM at 0x0
That also simplifies handling quite a bit.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:06:58 -05:00
Shirish S
bdbb4d6e96 drm/amdgpu: remove the intterupt handling for the KIQ events
[Why]
1. we never submit IBs to the KIQ
2. there seems to be ~500ms delay during amdgpu resume spent in KIQ,
   hence pointing toward interrupts are not working correctly.

[How]
remove interrupt handling for KIQ.

Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>i
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:06:26 -05:00
Felix Kuehling
1b19aa5aa8 drm/amdkfd: Fix incorrect use of process->mm
This mm_struct pointer should never be dereferenced. If running in
a user thread, just use current->mm. If running in a kernel worker
use get_task_mm to get a safe reference to the mm_struct.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Oded Gabbay <oded.gabbay@gmail.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-10-09 17:06:19 -05:00