Expose the SPICC gate clock to enable the SPICC controller.
Acked-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[tidy commit message to match similar changes]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Expose the spdif master clock and the mux to select the appropriate spdif
clock parent depending on the data source.
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Expose the clock gates required for the spdif output
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
This patch exports related BUS/VPU/RGA/HDCP/IEP/TSP/WIFI/
VIO/USB/EFUSE/GPU/CRYPTO clocks for dts reference.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
we use SCLK_TESTCLKOUT1 and SCLK_TESTCLKOUT2 for camera, so add those ids.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the bit locations that correspond to the USB clocks.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the GyroADC clock to the R8A7791 device tree.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
to me not catching up as quickly on patch review than anything else.
Overall it seems normal though, a few small changes to the core, mostly
small non-critical fixes here and there as well as driver updates for new
and existing hardware support. The biggest things are the TI clk driver
rework to lay the groundwork for clkctrl support in the next merge window
and the AmLogic audio/graphics clk support.
Core:
* clk_possible_parents debugfs file so we know which parents a clk
could possibly have
* Fix to make clk rate change notifiers stop on the first failure instead
of continuing
New Drivers:
* Mediatek MT6797 SoCs
* hi655x PMIC clks
* AmLogic Meson SoC i2s and spdif audio clks and Mali graphics clks
* Allwinner H5 SoCs and PRCM hardware
Updates:
* Nvidia Tegra T210 cleanups and non-critical fixes
* TI OMAP cleanups in preparation for clkctrl support
* Trivial fixes like kcalloc(), devm_* conversions, and seq_puts()
* ZTE zx296718 SoC VGA clks
* Rockchip clk-ids, fixups, and rename of rk1108 to rv1108
* Support for IDT VersaClock 5P49V5935
* Renesas R-Car H3 and M3-W IMR clks and ES2.0 rev of R-Car H3 support
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABCAAGBQJZE0YJAAoJEK0CiJfG5JUl9tEQAKVJx8VztYGt1REoFMtEEHmO
azhxT/uYGgdOMAr9a3mQxqfm5cJbjnb1EZj2RfC1XHs31BF66j40y9+5d8hY8Hzu
5IkY86s77TlqxGLwQcAsU75Q9cFrEW9X0KJ6OSzlrcc5hKlAEk/Z5lBKoQAm3mlU
JqD4DSyFqP0X3YSxV5R7yfarb/X3ekCiQ13EDrPRRhyvHUi6ReUJDDgbPHtA+O2c
ftLAARmxjzitzyvdXokXudkfNm8F5KePK+QkVikf6D/q+kx1D0BNJwZIjhpoiksn
z6LImLQ8l91AWghmqqpOFXolxQncPU+bJIL9Pox76p5b3EzbQuthIafiso8KsDST
4g3mHm42Yfx9uoF+U+pR8IeZfj5yQT91bvf8naPz/ngWMAlLP1IKJUvJN6jeTiwe
cO6GIec1OH40Xl7v/9EafMwDcnFG0cwQmzr/M6wi1dUlmbSygP9NOMTHlr6W/0wa
K2hCD6b5UHEgHmdfiJbZ2tKxLO0e8LABW+AU8fQH5S2eNe14vY0GvCzfAq5MArIz
QRpso/kdtGpTpwMEvV6PUmJ0IxYEjtNJVjGJYbORwios0SK0Xl6bJWf7gwn5crB6
nua9tVZtJEOHJS7S+ESp3VvuXj2/UGPoRRf5OsERo1S6ydGUQH+wDi1SJMdo/vtX
bIPzIw6WPxMp24JyKOhh
=/5a/
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"Sort of on the quieter side this time, which is probably due more to
me not catching up as quickly on patch review than anything else.
Overall it seems normal though, a few small changes to the core,
mostly small non-critical fixes here and there as well as driver
updates for new and existing hardware support.
The biggest things are the TI clk driver rework to lay the groundwork
for clkctrl support in the next merge window and the AmLogic
audio/graphics clk support.
Core:
- clk_possible_parents debugfs file so we know which parents a clk
could possibly have
- Fix to make clk rate change notifiers stop on the first failure
instead of continuing
New Drivers:
- Mediatek MT6797 SoCs
- hi655x PMIC clks
- AmLogic Meson SoC i2s and spdif audio clks and Mali graphics clks
- Allwinner H5 SoCs and PRCM hardware
Updates:
- Nvidia Tegra T210 cleanups and non-critical fixes
- TI OMAP cleanups in preparation for clkctrl support
- trivial fixes like kcalloc(), devm_* conversions, and seq_puts()
- ZTE zx296718 SoC VGA clks
- Rockchip clk-ids, fixups, and rename of rk1108 to rv1108
- IDT VersaClock 5P49V5935 support
- Renesas R-Car H3 and M3-W IMR clks and ES2.0 rev of R-Car H3
support"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (151 commits)
clk: x86: pmc-atom: Checking for IS_ERR() instead of NULL
clk: ti: divider: try to fix ti_clk_register_divider
clk: mvebu: Use kcalloc() in two functions
clk: mvebu: Use kcalloc() in of_cpu_clk_setup()
clk: nomadik: Delete error messages for a failed memory allocation in two functions
clk: nomadik: Use seq_puts() in nomadik_src_clk_show()
clk: Improve a size determination in two functions
clk: Replace four seq_printf() calls by seq_putc()
clk: si5351: Delete an error message for a failed memory allocation in si5351_i2c_probe()
clk: si5351: Use devm_kcalloc() in si5351_i2c_probe()
clk: at91: Use kcalloc() in of_at91_clk_pll_get_characteristics()
reset: mediatek: Add MT2701 ethsys reset controller include file
clk: mediatek: add mt2701 ethernet reset
clk: hi6220: Add the hi655x's pmic clock
clk: ti: fix building without legacy omap3
clk: ti: fix linker error with !SOC_OMAP4
clk: hi3620: Fix a typo in one variable name
clk: hi3620: Delete error messages for a failed memory allocation in two functions
clk: hi3620: Use kcalloc() in hi3620_mmc_clk_init()
clk: hisilicon: Delete error messages for failed memory allocations in hisi_clk_init()
...
Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch of smaller
changes, but also some new platforms that are worth mentioning:
* Rockchip RK3399 platforms for Chromebooks, including Samsung Chromebook
Plus (Kevin)
* Orange Pi PC2 (Allwinner H5)
* Freescale LS2088A and LS1088A SoCs
* Expanded support for Nvidia Tegra186 (and Jetson TX2)
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJZEA5TAAoJEIwa5zzehBx3uPwP/3NBPKvsDQha/x+PPgtSM1cM
pUEF1fxsLftrt+pUeRgMZqGE2xu5vVUKEQsr7KDdWMS9LMs50Pp9dTvfxr7A4Asm
WRRMR7Y3gPbr49uf4+JLLmn0hYXTeaoUftVneBj0qU9Flwe3mQDVULiRjPalWYVB
g0+NwkPE2lrqrudceA2HiVEXqNlVXCIh2mdMaC7Luo0VEsz7nRHT0TOGPaxnXB3M
NoJ56FPHtv3x9+C56B5CLJ/+Ya8SLgfqVwwoK8FgoqDzEF3nbhf/WCUyph+gHdP3
D+jMk7t0tvIW8Ne4TGXenoxBznZxgh5ObpLlKBKPCGJkKxpfuq9koH33MmY/WoUN
7uh3F3HI2sGr7tY/xaN8H7a9A4mHzipj8nqaAsjAJppIpioecGCFVtkY5q0jfxLC
aAc1o4zoimdPs9q9mu/qhgKNxWkoTYnwvtWHuwqEOggvSb1ulS1SPS24VkKrc4LI
XMGbA4mQOuFwZyG4FVfvWzbnhsHzDh4cgHaVGra6z5zoX1MUrvieCWEji+Ul1VWa
lUJ2sTilvSGkwjGcMUSki5p9GcU8dPXwqKiZqDuGx6Ps4aQsw0vz286BnBeVsusG
qLRH4nkqbF9xCEz9h71mcU6WMu17EsG9zMoCg5K4EZ+RIG3cgWq0dMWW1LqtRn7S
2YqayY3+UEyMPN146R1V
=q3Ix
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM 64-bit DT updates from Olof Johansson:
"Device-tree updates for arm64 platforms. Just as with 32-bit, a bunch
of smaller changes, but also some new platforms that are worth
mentioning:
- Rockchip RK3399 platforms for Chromebooks, including Samsung
Chromebook Plus (Kevin)
- Orange Pi PC2 (Allwinner H5)
- Freescale LS2088A and LS1088A SoCs
- Expanded support for Nvidia Tegra186 (and Jetson TX2)"
* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (180 commits)
arm64: dts: Add basic DT to support Spreadtrum's SP9860G
arm64: dts: exynos: Use - instead of @ for DT OPP entries
arm64: dts: exynos: Add support for s6e3hf2 panel device on TM2e board
arm64: dts: juno: add information about L1 and L2 caches
arm64: dts: juno: fix few unit address format warnings
arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB
arm64: marvell: dts: enable the crypto engine on the Armada 7040 DB
arm64: marvell: dts: add crypto engine description for 7k/8k
arm64: dts: marvell: add sdhci support for Armada 7K/8K
arm64: dts: marvell: add eMMC support for Armada 37xx
arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board
arm64: dts: hisi: add drive strength levels of the pins for Hi3660 SoC
arm64: dts: hisi: enable the NIC and SAS for the hip07-d05 board
arm64: dts: hisi: add SAS nodes for the hip07 SoC
arm64: dts: hisi: add RoCE nodes for the hip07 SoC
arm64: dts: hisi: add network related nodes for the hip07 SoC
arm64: dts: hisi: add mbigen nodes for the hip07 SoC
arm64: dts: rockchip: fix the memory size of PX5 Evaluation board
arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board
dt-bindings: arm: hisilicon: add bindings for hi3798cv200 SoC and Poplar board
...
Device-tree continues to see lots of updates. The majority of patches
here are smaller changes for new hardware on existing platforms, and
there are a few larger changes worth pointing out.
Major new platforms:
- Gemini has been ported to DT, so a handful of "new" platforms moved over
from board files
- Rockchip RK3288 support for Tinkerboard and Phytec phyCORE-RK3288 SoM and RDK
- A bunch of embedded platforms, several Linksys platforms, Synology DS116,
- Motorola Droid4 (really old OMAP-based phone) support is added.
Some refactorings, i.e. Allwinner H3/H5 support is commonalized.
And lots of smaller changes, cleanups, etc. See shortlog for more description
We're adding ability to cross-include DT files between arm and arm64,
by creating appropriate links in the dt-include directory, and using arm/
and arm64/ as include prefixes. This will avoid other local hacks such as
per-file links between the two arch trees (this broke for external mirroring
of DT contents). Now they can just provide their own appropriate dt-include
hierarcy per platform.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJZEAoxAAoJEIwa5zzehBx3li8P/iIMy0HmGuJ0JsTldMk4kgkM
1Ci/gcgKYn43m68RwvZCwkBxVibqCdMbBtLHCUt3ScGIYdj6mUG8axRHvFW/tsGf
BP0Y5pxm7l1BlHOKed97bJUeMyqqG13szzS7aB5L6cyZt41lAAkpCx4OFAuIlaxo
XM1v2xRSxqSf/zp4px83qX2hdHIpe4ZGlDiNh8rCBBnKMY4PqhK0V7TFLPOKbFnr
stIvD1TpvzacN67JVo1En0rCFgXSCwJ+CTumAOIx4tflV48ymY5THRNtI1ogFosc
1IfOxnC9DyRVM2ubFF7/ZLFbmn5KHu6ZwPLN+8Wl2McbT96PAtJ3h/zgTnuk4Tvf
GaAfqcyAXFeiZGU+bkkGiaQwXRDBroxVuNFTgERNgF70GUrDpBzd3tJO2rx7oZCS
Rj2QvKfBDBr9g5ldVGjOBIq/G9DeN5TtR6gyr/hCS/nm0NlYQ90Pzing0Nj8PDC9
/AOa4k4wUWo/oaFucBEeATCxto3TKpmBuP1I31sWG8StKVSJbIek2dSMcWSVFrG5
6/pzmuE4C7ZlshcFAUOeHxMVjBhTya5mDZQgZhCAnwhVMzrrpMTHTi27nbWcv/k8
9TH+ig5DoKL65FFE92ZkEb4S47SaD2+qKjEzJMDNQzc5WuY4l7pfDQoSn3YLjzKZ
xSKQEsmyOW0/0v8ecDKP
=v6w6
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM Device-tree updates from Olof Johansson:
"Device-tree continues to see lots of updates. The majority of patches
here are smaller changes for new hardware on existing platforms, and
there are a few larger changes worth pointing out.
Major new platforms:
- Gemini has been ported to DT, so a handful of "new" platforms moved
over from board files
- Rockchip RK3288 support for Tinkerboard and Phytec phyCORE-RK3288
SoM and RDK
- A bunch of embedded platforms, several Linksys platforms, Synology
DS116,
- Motorola Droid4 (really old OMAP-based phone) support is added.
Some refactorings, i.e. Allwinner H3/H5 support is commonalized.
And lots of smaller changes, cleanups, etc. See shortlog for more
description
We're adding ability to cross-include DT files between arm and arm64,
by creating appropriate links in the dt-include directory, and using
arm/ and arm64/ as include prefixes. This will avoid other local hacks
such as per-file links between the two arch trees (this broke for
external mirroring of DT contents). Now they can just provide their
own appropriate dt-include hierarcy per platform"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (349 commits)
ARM: dts: exynos: Use - instead of @ for DT OPP entries
arm: spear6xx: add DT description of the ADC on SPEAr600
arm: spear6xx: remove unneeded pinctrl properties in spear600-evb
arm: spear6xx: switch spear600-evb to the new flash partition DT binding
arm: spear6xx: fix spaces in spear600-evb.dts
arm: spear6xx: use node labels in spear600-evb.dts
arm: spear6xx: add labels to various nodes in spear600.dtsi
ARM: dts: vexpress: fix few unit address format warnings
ARM: dts: at91: sama5d3_xplained: not all ADC channels are available
ARM: dts: at91: sama5d3_xplained: fix ADC vref
ARM: dts: at91: add envelope detector mux to the Axentia TSE-850
ARM: dts: armada-38x: label USB and SATA nodes
ARM: dts: imx6q-utilite-pro: add hpd gpio
ARM: dts: imx6qp-sabresd: Set reg_arm regulator supply
ARM: dts: imx6qdl-sabresd: Set LDO regulator supply
ARM: dts: imx: add Gateworks Ventana GW5903 support
ARM: dts: i.MX25: add AIPS control registers
ARM: dts: imx7-colibri: add Carrier Board 3.3V/5V regulators
ARM: dts: imx7-colibri: remove 1.8V fixed regulator
ARM: dts: imx7-colibri: allow to disable Ethernet rail
...
Support for the new H5 SoC and the PRCM block found in a number of SoCs as
well, plus the usual chunk of fixes and minor enhancements.
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJY5feFAAoJEBx+YmzsjxAgzicP/2zx3xYRy5C69wI5IRxAMDjg
3AGgZgVXH/ir9CHVW7oGhBo9VdgbMdTZAJCA6WKBVjpjSsRkEVeEeRMTKAPbBBll
u5bFpQ2hX4WnGFlILAfXLtJJ39pEPZnHUN+ew3umR7xXMm76o7vB8Z59fd9qkgpP
wXwwZPDywtLusawxDjci0Wrzek8MHkFA6WwXnlnp82CbG+tLOe+o/x9kv125x9fT
td2POgaoG2FEBL1GyfqY0uzmNKs8oHwgbWmepsu5xFmmLYS4cwVHHIMAm3iOEmF+
tPZfeYxYVDY3cDfPhyj7/in3ej5SM63ZG6YSZjd2z/rXhGrcCNCmhFEwk9ie81oT
uHQ6B7K4hAtV1zJ7wZZJD/vqZewOaTcb/V9S7D1bGsBLcBrswOp7yaf2ECnhSQu0
C20Vp9xFdmSTReGIpD6+HCVLYSU0DHOVx0D/+dPOTtrfJR98xiEvUPekuo9yRmuc
MIBFzRJ83x9Ee5PS2jBju2V7VaGD08Q6R3JLDkCgUTaBTZq/jlNGc/9DD6llFM/E
idQ6j9dJnSzU6C4QVClIxBQHJu4kGNUUeWAXqxBTEh7jUg5bnKjUXox0W44RzqPP
j/ZWB60xLD/FdbaGQdxU72uFpok9Uc2fySvQqAwePe5F2j27IIMOKu/CpFmefc17
Ww+4lw2nbR3dypCxt6C7
=V49g
-----END PGP SIGNATURE-----
Merge tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next
Pull Allwinner clock patches for 4.12 from Maxime Ripard:
Support for the new H5 SoC and the PRCM block found in a number of SoCs as
well, plus the usual chunk of fixes and minor enhancements.
* tag 'sunxi-clk-for-4.12' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: Display index when clock registration fails
clk: sunxi-ng: a33: Add offset and minimum value for DDR1 PLL N factor
clk: sunxi-ng: a80: Remodel CPU cluster PLLs as N-type multiplier clocks
clk: sunxi-ng: mult: Support PLL lock detection
clk: sunxi-ng: add support for PRCM CCUs
dt-bindings: update device tree binding for Allwinner PRCM CCUs
clk: sunxi-ng: sun5i: Fix mux width for csi clock
clk: sunxi-ng: tighten SoC deps on explicit AllWinner SoCs
clk: sunxi-ng: add Allwinner H5 CCU support for H3 CCU driver
clk: sunxi-ng: gate: Support common pre-dividers
- meson8: add some new PLLs
- new clocks for Mali
- misc fixes.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJY5CeGAAoJEFk3GJrT+8Zlp8MP/01Po8BB0Hamo3SGIckzHIXn
4yYHnX4kYIGAHw4E1jki0Kz/3TxUSpUm4LWkcYloesPxnXipy2rlYJDhoFF1+QBM
A/Y6Tx9G6sTEmk/20HDzof7N1DzfGAdj+NJd3IMXaOIbP8XFBXgdRktB2kSUu0ZM
YPvlh5EjkWVhE5I+JqIfxSqAHW9+DOf17rhmch1wEXXMuVbtqPhm/DFd9+Ux+4WF
VoQ/dP0QLv0tszruJeI/bEqjgMGe+0feZt49aOpGuFfqVUP4tBs0fwOdjg6ELCrZ
Spw5GAewa7delQP8ihnC7n4wiV77k/qulReh4jExCt8s8L8nbkOL1naQlClMJfEb
RkoHC4MH0xxc9Q+J2l00DkHR7DgM2BTEUcmPvXkr+WBGJ+fN9gb3iIfJx9uY3DsD
W4iCkY+oAB7y4/lfa1LoImbGrrm9PmpXZR24TAkynaL2EOiQ7BtDuZsIFqu53VTn
O6UCIiKYlCtXrTzbpP/z6kbQ/8oASVE1hk1rfYSNpLU05KgCBFfS6pZWQDC8hJJv
UhK1nfxBrzIxQ130g9oJqFU5uwqheZJ4DLLBo751JLPfAPBI5tftxkHUOYWFA1+s
uoHZSDnKNiwnS+krjo2kFREF3etY/Fqp98OP2GYuP5H+MPsL1mIFxX/y/MBsDGwo
rH2TqHIyoKSPX5sIvS8I
=Tz8Z
-----END PGP SIGNATURE-----
Merge tag 'amlogic-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into clk-next
Same great taste as the previous pull request, but now with 50% less DT
bikeshedding!
Amlogic clock driver updates for v4.12
- meson8: add some new PLLs
- new clocks for Mali
- misc fixes.
as well as fixups of the clock-ids on rk3368 timers, which were unused
and completely wrong (more and differently named timers).
Also there is one new clock on rk3328 using the muxgrf type, a fix for
pll enablement which should wait for the pll to lock before continuing,
some more critical clocks and the rename of the rk1108 to rv1108, as the
soc seems to have been using a preliminary name before its actual release.
The plan is to have the driver changes (pinctrl, clk) go through the
respective maintainer trees and once everything landed in mainline do
the rename of the devicetree files. With the dts-include change in the
clock rename, we also keep everything compiling and thus bisectability.
-----BEGIN PGP SIGNATURE-----
iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAljY7X0QHGhlaWtvQHNu
dGVjaC5kZQAKCRDzpnnJnNEdgRKaCACXoa3hjtS3CSqyJZQyMPPQ0Oda7bblrubR
CE4GmuoZTnX/mUENFEmY7R+k0Np7b6ijPgdiFNpeZo0bpXAdi6bNjerG/QdRPV/P
yP9usSk/8Tx/kY7vnSNTve5QiIJDUoWKGY8fn7ped+GmM7Qeb3/QbWR4N/fL4vVD
nSZnKDO7yGMxLqWL0/QzZyiLzXl1ViEkPWFTedMf3cm0A48p8M/K5jinfMvl9I+o
6e2TIsc2zn6vRKuoGhjqcaRxhtRRV9c2O8wVAcA6BLo/kk3pA9ZTU3QJPsqEcN6A
BTbANYfXiQF6i+Xp1YJHcE2lNQ/sWZOTQtLqY9SL5WzMETMTETT5
=In5R
-----END PGP SIGNATURE-----
Merge tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk driver updates from Heiko Stuebner:
General rockchip clock changes for 4.12. Contains some new clock-ids
as well as fixups of the clock-ids on rk3368 timers, which were unused
and completely wrong (more and differently named timers).
Also there is one new clock on rk3328 using the muxgrf type, a fix for
pll enablement which should wait for the pll to lock before continuing,
some more critical clocks and the rename of the rk1108 to rv1108, as the
soc seems to have been using a preliminary name before its actual release.
The plan is to have the driver changes (pinctrl, clk) go through the
respective maintainer trees and once everything landed in mainline do
the rename of the devicetree files. With the dts-include change in the
clock rename, we also keep everything compiling and thus bisectability.
* tag 'v4.12-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: add pll_wait_lock for pll_enable
clk: rockchip: rename RK1108 to RV1108
dt-bindings: rk1108-cru: rename RK1108 to RV1108
clk: rockchip: mark some rk3368 core-clks as critical
clk: rockchip: export SCLK_TIMERXX id for timers on rk3368
clk: rockchip: describe clk_gmac using the new muxgrf type on rk3328
clk: rockchip: add clock ids for timer10-15 of RK3368 SoCs
clk: rockchip: fix up rk3368 timer-ids
clk: rockchip: add rk3328 clk_mac2io_ext ID
clk: rockchip: Set "ignore unused" for PMU M0 clocks on rk3399
- Add support for the Clock Pulse Generator / Module Standby and
Software Reset module on revision ES2.0 of the R-Car H3 SoC, which
differs from ES1.x in some areas.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJY3h3eAAoJEEgEtLw/Ve77F5MP/REcR7bb9TmdCDwXFpMXmZtw
jigpASslArlBsBfWsGX3oalkrrKLY+qs8d8++9+OIYdvf6stFNEH5E0PoOTOmNGY
bs6NnXNXxKoRIe/HK2bXYav2MAmf2fDNWFSnWapygV9j8CjudCEPrK+GZcWI+0ED
Sy5zE/exnPb/oZp5VutzZNiCAuI79iXjtIDOZDidQxwzC/AOQ2wq99ieclEafABX
F5XQkUtYjEzu7DgX2Luy0f7GMlNCVlaYbM1oi41Reka9UF8Ei3G7tLX+/qNgkyu3
U6HMRbiQBkOKVBAfKetmOyAJxhHk1R+Q6e9Qm3LJqHVt9Ar9nclybEcRMcYMJFpB
aF9mehg0U/3yyX3IW7arXTCLegSPsOLn+Hgo1b8tG2BZKsMQrd86elVVGPODkDZj
CQyge358wvMKzqTozGjP9s8TetU0lpQI7HrK0/X0dNmYnJlejJ0mi3cSUu+Rp8al
+tbMJL47W3JxBFhh1kBJGMoUW3glbDYdlwyvGy/Fsl84TCWD6bmKh8AhRQrYbOR8
Jo3CiH22HPHAT0TWXwOhEuB6TxDacpA7Wf0dDN0EPRZ2kGrRvjvxv7zg8BPKCGcA
G6uTX+Wlov8TTwYzluLtfbbRS0Kmcx0ZcuKAmgoV9991e4IC6YKaBok4ArqfEdwR
BcnSkpRriiVRqbj17Hdi
=rttL
-----END PGP SIGNATURE-----
Merge tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next
Pull Renesas clk driver updates from Geert Uytterhoeven:
- Add support for the Clock Pulse Generator / Module Standby and
Software Reset module on revision ES2.0 of the R-Car H3 SoC, which
differs from ES1.x in some areas.
- Add IMR clocks for R-Car H3 and M3-W,
- Add workaround for PLL0/2/4 errata on R-Car H3 ES1.0,
- Small fixes and cleanups.
* tag 'clk-renesas-for-v4.12-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0
clk: renesas: r8a7795: Add support for R-Car H3 ES2.0
clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions
clk: renesas: cpg-mssr: Add support for fixing up clock tables
clk: renesas: rcar-gen3: Add workaround for PLL0/2/4 errata on H3 ES1.0
clk: renesas: rcar-gen3-cpg: Pass mode pins to rcar_gen3_cpg_init()
clk: renesas: r8a7796: Reformat core clock table
clk: renesas: r8a7795: Reformat core clock table
clk: renesas: r8a7796: Correct name of watchdog clock
clk: renesas: r8a7795: Correct name of watchdog clock
clk: renesas: r8a7795: Correct parent clock and sort order for Audio DMACs
clk: renesas: r8a7796: Add IMR clocks
clk: renesas: r8a7795: Add IMR clocks
The debug APB clock is absent in hi6220 driver, so this patch is to add
support for it.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
SoCs after A31 has a clock controller module in the PRCM part.
Support the clock controller module on H3/5 and A64 now.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
iqc1, iqc2, tegra_clk_pll_a_out_adsp, tegra_clk_pll_a_out0_out_adsp, adsp
and adsp neon were not modelled. dp2 wasn't modelled for Tegra210.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Unlike other R-Car Gen2 SoCs with Cortex-A15 CPU cores, R-Car V2H does
not have a programmable Z clock (Cortex-A15 CPU core clock), but uses a
fixed divider.
This is similar to the Z2 clock (Cortex-A7 CPU core clock) on R-Car E2.
Hence:
- Remove the Z clock output from the cpg_clocks node, as this implied
a programmable clock,
- Add the Z clock as a fixed factor clock,
- Let the first CPU node point to the new Z clock,
- Remove the Z clock index from the bindings (this definition was used
by r8a7792.dtsi only, and was not a contract between DT and driver).
Fixes: 7c4163aae3 ("ARM: dts: r8a7792: initial SoC device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the missing module clock for the second channel of the display unit.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Rockchip finally named the SOC as RV1108, so change it.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
[include rename in rk1108.dtsi to prevent compile errors]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This clock clocks the ADSP Cortex-A9.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra210 has 3 DMIC inputs which can be clocked from the recovered clock
of several other audio inputs (eg. i2s0, i2s1, ...). To model this, we
add a 3 new clocks similar to the audio* clocks which handle the same
function for the I2S and SPDIF clocks.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This clock is used to clock the HDMI CEC interface.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The 2 ISP clocks (ispa and ispb) share a mux/divider control. So model
this as 1 mux/divider clock and child gate clocks.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Expose clock CLKID_RNG0 which is needed for the HW random number generator.
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always
on" PM Domain, so it can be power managed using that clock.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The timer-ids are wrong compared to the manual, probably due a simple
copy-paste mistake from the otherwise very similar rk3288. And there
are even more timers in the system than the ones wrongly listed here.
Timer-Ids were unused both in clock-driver as well as devicetree
till now, so fixing them won't break anything.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always
on" PM Domain, so it can be power managed using that clock.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always
on" PM Domain, so it can be power managed using that clock.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always
on" PM Domain, so it can be power managed using that clock.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link the ARM GIC to the INTC-SYS module clock, and add it to the "always
on" PM Domain, so it can be power managed using that clock.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Link the ARM GIC to the INTC-SYS module clock and the C4 power domain,
so it can be power managed using that clock in the future.
Note that currently the GIC-400 driver doesn't support module clocks nor
Runtime PM, so this must be handled as a critical clock.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Allwinner H5 is a SoC that features a design which keeps the peripheral
compatible with H3, so that it have also a CCU like the one on H3 --
only one bus gate/reset is added, and the mmc sample/output phases are
removed because of MMC controller update.
Add its support in our existing H3 CCU driver.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The SDHI controller in the RZ/A1 has 2 clock sources per channel and both
need to be enabled/disabled for proper operation. This fixes the fact that
the define for R7S72100_CLK_SDHI1 was not correct to begin with (typo), and
that all 4 clock sources need to be defined an used.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
