mirror of
https://gitee.com/bianbu-linux/linux-6.6
synced 2025-04-26 14:17:26 -04:00
40319796b7
Add support to enable flow-director filter when multiple TCs are configured. Flow director filter can be configured using ethtool (--config-ntuple option). When multiple TCs are configured, each TC is mapped to an unique HW VSI. So VSI corresponding to queue used in filter is identified and flow director context is updated with correct VSI while configuring ntuple filter in HW. Signed-off-by: Kiran Patil <kiran.patil@intel.com> Signed-off-by: Amritha Nambiar <amritha.nambiar@intel.com> Signed-off-by: Sudheer Mogilappagari <sudheer.mogilappagari@intel.com> Tested-by: Bharathi Sreenivas <bharathi.sreenivas@intel.com> Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
414 lines
14 KiB
C
414 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2019, Intel Corporation. */
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#ifndef _ICE_FLOW_H_
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#define _ICE_FLOW_H_
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#define ICE_FLOW_ENTRY_HANDLE_INVAL 0
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#define ICE_FLOW_FLD_OFF_INVAL 0xffff
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/* Generate flow hash field from flow field type(s) */
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#define ICE_FLOW_HASH_ETH \
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(BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_DA) | \
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BIT_ULL(ICE_FLOW_FIELD_IDX_ETH_SA))
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#define ICE_FLOW_HASH_IPV4 \
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(BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
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BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))
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#define ICE_FLOW_HASH_IPV6 \
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(BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA) | \
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BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA))
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#define ICE_FLOW_HASH_TCP_PORT \
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(BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_SRC_PORT) | \
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BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT))
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#define ICE_FLOW_HASH_UDP_PORT \
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(BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT) | \
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BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT))
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#define ICE_FLOW_HASH_SCTP_PORT \
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(BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT) | \
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BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_DST_PORT))
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#define ICE_HASH_INVALID 0
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#define ICE_HASH_TCP_IPV4 (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_TCP_PORT)
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#define ICE_HASH_TCP_IPV6 (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_TCP_PORT)
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#define ICE_HASH_UDP_IPV4 (ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_UDP_PORT)
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#define ICE_HASH_UDP_IPV6 (ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_UDP_PORT)
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#define ICE_FLOW_HASH_GTP_TEID \
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(BIT_ULL(ICE_FLOW_FIELD_IDX_GTPC_TEID))
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#define ICE_FLOW_HASH_GTP_IPV4_TEID \
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(ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_GTP_TEID)
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#define ICE_FLOW_HASH_GTP_IPV6_TEID \
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(ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_GTP_TEID)
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#define ICE_FLOW_HASH_GTP_U_TEID \
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(BIT_ULL(ICE_FLOW_FIELD_IDX_GTPU_IP_TEID))
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#define ICE_FLOW_HASH_GTP_U_IPV4_TEID \
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(ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_GTP_U_TEID)
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#define ICE_FLOW_HASH_GTP_U_IPV6_TEID \
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(ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_GTP_U_TEID)
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#define ICE_FLOW_HASH_GTP_U_EH_TEID \
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(BIT_ULL(ICE_FLOW_FIELD_IDX_GTPU_EH_TEID))
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#define ICE_FLOW_HASH_GTP_U_EH_QFI \
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(BIT_ULL(ICE_FLOW_FIELD_IDX_GTPU_EH_QFI))
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#define ICE_FLOW_HASH_GTP_U_IPV4_EH \
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(ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_GTP_U_EH_TEID | \
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ICE_FLOW_HASH_GTP_U_EH_QFI)
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#define ICE_FLOW_HASH_GTP_U_IPV6_EH \
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(ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_GTP_U_EH_TEID | \
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ICE_FLOW_HASH_GTP_U_EH_QFI)
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#define ICE_FLOW_HASH_PPPOE_SESS_ID \
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(BIT_ULL(ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID))
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#define ICE_FLOW_HASH_PPPOE_SESS_ID_ETH \
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(ICE_FLOW_HASH_ETH | ICE_FLOW_HASH_PPPOE_SESS_ID)
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#define ICE_FLOW_HASH_PPPOE_TCP_ID \
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(ICE_FLOW_HASH_TCP_PORT | ICE_FLOW_HASH_PPPOE_SESS_ID)
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#define ICE_FLOW_HASH_PPPOE_UDP_ID \
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(ICE_FLOW_HASH_UDP_PORT | ICE_FLOW_HASH_PPPOE_SESS_ID)
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#define ICE_FLOW_HASH_PFCP_SEID \
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(BIT_ULL(ICE_FLOW_FIELD_IDX_PFCP_SEID))
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#define ICE_FLOW_HASH_PFCP_IPV4_SEID \
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(ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_PFCP_SEID)
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#define ICE_FLOW_HASH_PFCP_IPV6_SEID \
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(ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_PFCP_SEID)
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#define ICE_FLOW_HASH_L2TPV3_SESS_ID \
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(BIT_ULL(ICE_FLOW_FIELD_IDX_L2TPV3_SESS_ID))
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#define ICE_FLOW_HASH_L2TPV3_IPV4_SESS_ID \
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(ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_L2TPV3_SESS_ID)
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#define ICE_FLOW_HASH_L2TPV3_IPV6_SESS_ID \
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(ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_L2TPV3_SESS_ID)
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#define ICE_FLOW_HASH_ESP_SPI \
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(BIT_ULL(ICE_FLOW_FIELD_IDX_ESP_SPI))
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#define ICE_FLOW_HASH_ESP_IPV4_SPI \
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(ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_ESP_SPI)
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#define ICE_FLOW_HASH_ESP_IPV6_SPI \
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(ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_ESP_SPI)
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#define ICE_FLOW_HASH_AH_SPI \
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(BIT_ULL(ICE_FLOW_FIELD_IDX_AH_SPI))
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#define ICE_FLOW_HASH_AH_IPV4_SPI \
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(ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_AH_SPI)
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#define ICE_FLOW_HASH_AH_IPV6_SPI \
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(ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_AH_SPI)
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#define ICE_FLOW_HASH_NAT_T_ESP_SPI \
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(BIT_ULL(ICE_FLOW_FIELD_IDX_NAT_T_ESP_SPI))
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#define ICE_FLOW_HASH_NAT_T_ESP_IPV4_SPI \
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(ICE_FLOW_HASH_IPV4 | ICE_FLOW_HASH_NAT_T_ESP_SPI)
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#define ICE_FLOW_HASH_NAT_T_ESP_IPV6_SPI \
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(ICE_FLOW_HASH_IPV6 | ICE_FLOW_HASH_NAT_T_ESP_SPI)
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/* Protocol header fields within a packet segment. A segment consists of one or
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* more protocol headers that make up a logical group of protocol headers. Each
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* logical group of protocol headers encapsulates or is encapsulated using/by
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* tunneling or encapsulation protocols for network virtualization such as GRE,
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* VxLAN, etc.
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*/
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enum ice_flow_seg_hdr {
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ICE_FLOW_SEG_HDR_NONE = 0x00000000,
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ICE_FLOW_SEG_HDR_ETH = 0x00000001,
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ICE_FLOW_SEG_HDR_VLAN = 0x00000002,
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ICE_FLOW_SEG_HDR_IPV4 = 0x00000004,
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ICE_FLOW_SEG_HDR_IPV6 = 0x00000008,
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ICE_FLOW_SEG_HDR_ARP = 0x00000010,
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ICE_FLOW_SEG_HDR_ICMP = 0x00000020,
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ICE_FLOW_SEG_HDR_TCP = 0x00000040,
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ICE_FLOW_SEG_HDR_UDP = 0x00000080,
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ICE_FLOW_SEG_HDR_SCTP = 0x00000100,
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ICE_FLOW_SEG_HDR_GRE = 0x00000200,
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ICE_FLOW_SEG_HDR_GTPC = 0x00000400,
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ICE_FLOW_SEG_HDR_GTPC_TEID = 0x00000800,
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ICE_FLOW_SEG_HDR_GTPU_IP = 0x00001000,
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ICE_FLOW_SEG_HDR_GTPU_EH = 0x00002000,
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ICE_FLOW_SEG_HDR_GTPU_DWN = 0x00004000,
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ICE_FLOW_SEG_HDR_GTPU_UP = 0x00008000,
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ICE_FLOW_SEG_HDR_PPPOE = 0x00010000,
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ICE_FLOW_SEG_HDR_PFCP_NODE = 0x00020000,
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ICE_FLOW_SEG_HDR_PFCP_SESSION = 0x00040000,
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ICE_FLOW_SEG_HDR_L2TPV3 = 0x00080000,
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ICE_FLOW_SEG_HDR_ESP = 0x00100000,
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ICE_FLOW_SEG_HDR_AH = 0x00200000,
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ICE_FLOW_SEG_HDR_NAT_T_ESP = 0x00400000,
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ICE_FLOW_SEG_HDR_ETH_NON_IP = 0x00800000,
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/* The following is an additive bit for ICE_FLOW_SEG_HDR_IPV4 and
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* ICE_FLOW_SEG_HDR_IPV6 which include the IPV4 other PTYPEs
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*/
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ICE_FLOW_SEG_HDR_IPV_OTHER = 0x20000000,
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};
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/* These segments all have the same PTYPES, but are otherwise distinguished by
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* the value of the gtp_eh_pdu and gtp_eh_pdu_link flags:
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*
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* gtp_eh_pdu gtp_eh_pdu_link
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* ICE_FLOW_SEG_HDR_GTPU_IP 0 0
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* ICE_FLOW_SEG_HDR_GTPU_EH 1 don't care
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* ICE_FLOW_SEG_HDR_GTPU_DWN 1 0
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* ICE_FLOW_SEG_HDR_GTPU_UP 1 1
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*/
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#define ICE_FLOW_SEG_HDR_GTPU (ICE_FLOW_SEG_HDR_GTPU_IP | \
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ICE_FLOW_SEG_HDR_GTPU_EH | \
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ICE_FLOW_SEG_HDR_GTPU_DWN | \
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ICE_FLOW_SEG_HDR_GTPU_UP)
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#define ICE_FLOW_SEG_HDR_PFCP (ICE_FLOW_SEG_HDR_PFCP_NODE | \
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ICE_FLOW_SEG_HDR_PFCP_SESSION)
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enum ice_flow_field {
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/* L2 */
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ICE_FLOW_FIELD_IDX_ETH_DA,
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ICE_FLOW_FIELD_IDX_ETH_SA,
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ICE_FLOW_FIELD_IDX_S_VLAN,
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ICE_FLOW_FIELD_IDX_C_VLAN,
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ICE_FLOW_FIELD_IDX_ETH_TYPE,
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/* L3 */
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ICE_FLOW_FIELD_IDX_IPV4_DSCP,
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ICE_FLOW_FIELD_IDX_IPV6_DSCP,
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ICE_FLOW_FIELD_IDX_IPV4_TTL,
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ICE_FLOW_FIELD_IDX_IPV4_PROT,
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ICE_FLOW_FIELD_IDX_IPV6_TTL,
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ICE_FLOW_FIELD_IDX_IPV6_PROT,
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ICE_FLOW_FIELD_IDX_IPV4_SA,
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ICE_FLOW_FIELD_IDX_IPV4_DA,
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ICE_FLOW_FIELD_IDX_IPV6_SA,
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ICE_FLOW_FIELD_IDX_IPV6_DA,
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/* L4 */
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ICE_FLOW_FIELD_IDX_TCP_SRC_PORT,
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ICE_FLOW_FIELD_IDX_TCP_DST_PORT,
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ICE_FLOW_FIELD_IDX_UDP_SRC_PORT,
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ICE_FLOW_FIELD_IDX_UDP_DST_PORT,
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ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT,
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ICE_FLOW_FIELD_IDX_SCTP_DST_PORT,
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ICE_FLOW_FIELD_IDX_TCP_FLAGS,
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/* ARP */
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ICE_FLOW_FIELD_IDX_ARP_SIP,
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ICE_FLOW_FIELD_IDX_ARP_DIP,
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ICE_FLOW_FIELD_IDX_ARP_SHA,
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ICE_FLOW_FIELD_IDX_ARP_DHA,
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ICE_FLOW_FIELD_IDX_ARP_OP,
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/* ICMP */
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ICE_FLOW_FIELD_IDX_ICMP_TYPE,
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ICE_FLOW_FIELD_IDX_ICMP_CODE,
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/* GRE */
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ICE_FLOW_FIELD_IDX_GRE_KEYID,
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/* GTPC_TEID */
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ICE_FLOW_FIELD_IDX_GTPC_TEID,
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/* GTPU_IP */
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ICE_FLOW_FIELD_IDX_GTPU_IP_TEID,
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/* GTPU_EH */
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ICE_FLOW_FIELD_IDX_GTPU_EH_TEID,
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ICE_FLOW_FIELD_IDX_GTPU_EH_QFI,
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/* GTPU_UP */
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ICE_FLOW_FIELD_IDX_GTPU_UP_TEID,
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/* GTPU_DWN */
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ICE_FLOW_FIELD_IDX_GTPU_DWN_TEID,
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/* PPPoE */
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ICE_FLOW_FIELD_IDX_PPPOE_SESS_ID,
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/* PFCP */
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ICE_FLOW_FIELD_IDX_PFCP_SEID,
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/* L2TPv3 */
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ICE_FLOW_FIELD_IDX_L2TPV3_SESS_ID,
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/* ESP */
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ICE_FLOW_FIELD_IDX_ESP_SPI,
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/* AH */
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ICE_FLOW_FIELD_IDX_AH_SPI,
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/* NAT_T ESP */
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ICE_FLOW_FIELD_IDX_NAT_T_ESP_SPI,
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/* The total number of enums must not exceed 64 */
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ICE_FLOW_FIELD_IDX_MAX
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};
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/* Flow headers and fields for AVF support */
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enum ice_flow_avf_hdr_field {
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/* Values 0 - 28 are reserved for future use */
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ICE_AVF_FLOW_FIELD_INVALID = 0,
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ICE_AVF_FLOW_FIELD_UNICAST_IPV4_UDP = 29,
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ICE_AVF_FLOW_FIELD_MULTICAST_IPV4_UDP,
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ICE_AVF_FLOW_FIELD_IPV4_UDP,
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ICE_AVF_FLOW_FIELD_IPV4_TCP_SYN_NO_ACK,
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ICE_AVF_FLOW_FIELD_IPV4_TCP,
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ICE_AVF_FLOW_FIELD_IPV4_SCTP,
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ICE_AVF_FLOW_FIELD_IPV4_OTHER,
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ICE_AVF_FLOW_FIELD_FRAG_IPV4,
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/* Values 37-38 are reserved */
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ICE_AVF_FLOW_FIELD_UNICAST_IPV6_UDP = 39,
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ICE_AVF_FLOW_FIELD_MULTICAST_IPV6_UDP,
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ICE_AVF_FLOW_FIELD_IPV6_UDP,
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ICE_AVF_FLOW_FIELD_IPV6_TCP_SYN_NO_ACK,
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ICE_AVF_FLOW_FIELD_IPV6_TCP,
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ICE_AVF_FLOW_FIELD_IPV6_SCTP,
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ICE_AVF_FLOW_FIELD_IPV6_OTHER,
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ICE_AVF_FLOW_FIELD_FRAG_IPV6,
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ICE_AVF_FLOW_FIELD_RSVD47,
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ICE_AVF_FLOW_FIELD_FCOE_OX,
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ICE_AVF_FLOW_FIELD_FCOE_RX,
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ICE_AVF_FLOW_FIELD_FCOE_OTHER,
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/* Values 51-62 are reserved */
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ICE_AVF_FLOW_FIELD_L2_PAYLOAD = 63,
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ICE_AVF_FLOW_FIELD_MAX
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};
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/* Supported RSS offloads This macro is defined to support
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* VIRTCHNL_OP_GET_RSS_HENA_CAPS ops. PF driver sends the RSS hardware
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* capabilities to the caller of this ops.
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*/
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#define ICE_DEFAULT_RSS_HENA ( \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_UDP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_SCTP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_TCP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_OTHER) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_FRAG_IPV4) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_UDP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_TCP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_SCTP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_OTHER) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_FRAG_IPV6) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_TCP_SYN_NO_ACK) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_UNICAST_IPV4_UDP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_MULTICAST_IPV4_UDP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_TCP_SYN_NO_ACK) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_UNICAST_IPV6_UDP) | \
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BIT_ULL(ICE_AVF_FLOW_FIELD_MULTICAST_IPV6_UDP))
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enum ice_flow_dir {
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ICE_FLOW_RX = 0x02,
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};
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enum ice_flow_priority {
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ICE_FLOW_PRIO_LOW,
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ICE_FLOW_PRIO_NORMAL,
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ICE_FLOW_PRIO_HIGH
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};
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#define ICE_FLOW_SEG_MAX 2
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#define ICE_FLOW_SEG_RAW_FLD_MAX 2
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#define ICE_FLOW_FV_EXTRACT_SZ 2
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#define ICE_FLOW_SET_HDRS(seg, val) ((seg)->hdrs |= (u32)(val))
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struct ice_flow_seg_xtrct {
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u8 prot_id; /* Protocol ID of extracted header field */
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u16 off; /* Starting offset of the field in header in bytes */
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u8 idx; /* Index of FV entry used */
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u8 disp; /* Displacement of field in bits fr. FV entry's start */
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u16 mask; /* Mask for field */
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};
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enum ice_flow_fld_match_type {
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ICE_FLOW_FLD_TYPE_REG, /* Value, mask */
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ICE_FLOW_FLD_TYPE_RANGE, /* Value, mask, last (upper bound) */
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ICE_FLOW_FLD_TYPE_PREFIX, /* IP address, prefix, size of prefix */
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ICE_FLOW_FLD_TYPE_SIZE, /* Value, mask, size of match */
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};
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struct ice_flow_fld_loc {
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/* Describe offsets of field information relative to the beginning of
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* input buffer provided when adding flow entries.
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*/
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u16 val; /* Offset where the value is located */
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u16 mask; /* Offset where the mask/prefix value is located */
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u16 last; /* Length or offset where the upper value is located */
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};
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struct ice_flow_fld_info {
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enum ice_flow_fld_match_type type;
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/* Location where to retrieve data from an input buffer */
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struct ice_flow_fld_loc src;
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/* Location where to put the data into the final entry buffer */
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struct ice_flow_fld_loc entry;
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struct ice_flow_seg_xtrct xtrct;
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};
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struct ice_flow_seg_fld_raw {
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struct ice_flow_fld_info info;
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u16 off; /* Offset from the start of the segment */
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};
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struct ice_flow_seg_info {
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u32 hdrs; /* Bitmask indicating protocol headers present */
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u64 match; /* Bitmask indicating header fields to be matched */
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u64 range; /* Bitmask indicating header fields matched as ranges */
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struct ice_flow_fld_info fields[ICE_FLOW_FIELD_IDX_MAX];
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u8 raws_cnt; /* Number of raw fields to be matched */
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struct ice_flow_seg_fld_raw raws[ICE_FLOW_SEG_RAW_FLD_MAX];
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};
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/* This structure describes a flow entry, and is tracked only in this file */
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struct ice_flow_entry {
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struct list_head l_entry;
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u64 id;
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struct ice_flow_prof *prof;
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/* Flow entry's content */
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void *entry;
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enum ice_flow_priority priority;
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u16 vsi_handle;
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u16 entry_sz;
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};
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#define ICE_FLOW_ENTRY_HNDL(e) ((u64)(uintptr_t)e)
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#define ICE_FLOW_ENTRY_PTR(h) ((struct ice_flow_entry *)(uintptr_t)(h))
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struct ice_flow_prof {
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struct list_head l_entry;
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|
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u64 id;
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enum ice_flow_dir dir;
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u8 segs_cnt;
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|
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/* Keep track of flow entries associated with this flow profile */
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struct mutex entries_lock;
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struct list_head entries;
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|
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struct ice_flow_seg_info segs[ICE_FLOW_SEG_MAX];
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|
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/* software VSI handles referenced by this flow profile */
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DECLARE_BITMAP(vsis, ICE_MAX_VSI);
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};
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|
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|
struct ice_rss_cfg {
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struct list_head l_entry;
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/* bitmap of VSIs added to the RSS entry */
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|
DECLARE_BITMAP(vsis, ICE_MAX_VSI);
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|
u64 hashed_flds;
|
|
u32 packet_hdr;
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|
};
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|
|
|
int
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ice_flow_add_prof(struct ice_hw *hw, enum ice_block blk, enum ice_flow_dir dir,
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u64 prof_id, struct ice_flow_seg_info *segs, u8 segs_cnt,
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struct ice_flow_prof **prof);
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int ice_flow_rem_prof(struct ice_hw *hw, enum ice_block blk, u64 prof_id);
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int
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ice_flow_add_entry(struct ice_hw *hw, enum ice_block blk, u64 prof_id,
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u64 entry_id, u16 vsi, enum ice_flow_priority prio,
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|
void *data, u64 *entry_h);
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int ice_flow_rem_entry(struct ice_hw *hw, enum ice_block blk, u64 entry_h);
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|
void
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|
ice_flow_set_fld(struct ice_flow_seg_info *seg, enum ice_flow_field fld,
|
|
u16 val_loc, u16 mask_loc, u16 last_loc, bool range);
|
|
void
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ice_flow_add_fld_raw(struct ice_flow_seg_info *seg, u16 off, u8 len,
|
|
u16 val_loc, u16 mask_loc);
|
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int ice_flow_rem_vsi_prof(struct ice_hw *hw, u16 vsi_handle, u64 prof_id);
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|
void ice_rem_vsi_rss_list(struct ice_hw *hw, u16 vsi_handle);
|
|
int ice_replay_rss_cfg(struct ice_hw *hw, u16 vsi_handle);
|
|
int ice_add_avf_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds);
|
|
int ice_rem_vsi_rss_cfg(struct ice_hw *hw, u16 vsi_handle);
|
|
int
|
|
ice_add_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
|
|
u32 addl_hdrs);
|
|
int
|
|
ice_rem_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u64 hashed_flds,
|
|
u32 addl_hdrs);
|
|
u64 ice_get_rss_cfg(struct ice_hw *hw, u16 vsi_handle, u32 hdrs);
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|
#endif /* _ICE_FLOW_H_ */
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