Hugo Hu 132c894e93 drm/amd/display: treat memory as a single-channel for asymmetric memory V3 ... Previous patch caused crash and had been reverted. This patch addresses the issue without regression. [Why] 1. Driver use umachannelnumber to calculate watermarks for stutter. In asymmetric memory config, the actual bandwidth is less than dual-channel. The bandwidth should be the same as single-channel. 2. We found single rank dimm need additional delay time for stutter. [How] Get information from each DIMM. Treat memory config as a single-channel for asymmetric memory in bandwidth calculating. Add additional delay time for single rank dimm. Signed-off-by: Hugo Hu <hugo.hu@amd.com> Reviewed-by: Sung Lee <Sung.Lee@amd.com> Acked-by: Stylon Wang <stylon.wang@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2021-05-19 22:38:24 -04:00
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dce60	drm/amd/display: dc/clk_mgr: make function static	2020-09-17 21:21:40 -04:00
dce100	drm/amd/display: remove redundant assignment to variable dp_ref_clk_khz	2020-04-22 18:11:45 -04:00
dce110	drm/amd/display: correct asic type check V2	2020-10-27 12:01:16 -04:00
dce112	drm/amd/display: correct asic type check V2	2020-10-27 12:01:16 -04:00
dce120	drm/amd/display: Copy max_clks_by_state after dce_clk_mgr_construct	2019-07-18 14:18:09 -05:00
dcn10	Revert "drm/amd/display: Tune min clk values for MPO for RV"	2021-01-25 17:45:21 -05:00
dcn20	drm/amd/display: Fix typo when retrieving dppclk from UEFI config	2021-03-23 23:02:23 -04:00
dcn21	drm/amd/display: treat memory as a single-channel for asymmetric memory V3	2021-05-19 22:38:24 -04:00
dcn30	drm/amd/display: Fixed typo in function name.	2021-04-20 21:42:05 -04:00
dcn301	drm/amd/display: Add dc_debug flag to disable min fclk	2021-04-09 16:51:59 -04:00
clk_mgr.c	drm/amdgpu/display: fix memory leak for dimgrey cavefish	2021-04-09 16:42:32 -04:00
Makefile	drm/amdgpu/display: drop DCN support for aarch64	2021-01-05 11:35:53 -05:00