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https://gitee.com/bianbu-linux/linux-6.6
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0e862838f2
Currently, there is a mess with the prototypes of the non-atomic bitops across the different architectures: ret bool, int, unsigned long nr int, long, unsigned int, unsigned long addr volatile unsigned long *, volatile void * Thankfully, it doesn't provoke any bugs, but can sometimes make the compiler angry when it's not handy at all. Adjust all the prototypes to the following standard: ret bool retval can be only 0 or 1 nr unsigned long native; signed makes no sense addr volatile unsigned long * bitmaps are arrays of ulongs Next, some architectures don't define 'arch_' versions as they don't support instrumentation, others do. To make sure there is always the same set of callables present and to ease any potential future changes, make them all follow the rule: * architecture-specific files define only 'arch_' versions; * non-prefixed versions can be defined only in asm-generic files; and place the non-prefixed definitions into a new file in asm-generic to be included by non-instrumented architectures. Finally, add some static assertions in order to prevent people from making a mess in this room again. I also used the %__always_inline attribute consistently, so that they always get resolved to the actual operations. Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Alexander Lobakin <alexandr.lobakin@intel.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Yury Norov <yury.norov@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Yury Norov <yury.norov@gmail.com>
289 lines
6.1 KiB
C
289 lines
6.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Bit operations for the Hexagon architecture
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*
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* Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
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*/
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#ifndef _ASM_BITOPS_H
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#define _ASM_BITOPS_H
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#include <linux/compiler.h>
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#include <asm/byteorder.h>
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#include <asm/atomic.h>
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#include <asm/barrier.h>
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#ifdef __KERNEL__
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/*
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* The offset calculations for these are based on BITS_PER_LONG == 32
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* (i.e. I get to shift by #5-2 (32 bits per long, 4 bytes per access),
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* mask by 0x0000001F)
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*
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* Typically, R10 is clobbered for address, R11 bit nr, and R12 is temp
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*/
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/**
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* test_and_clear_bit - clear a bit and return its old value
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* @nr: bit number to clear
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* @addr: pointer to memory
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*/
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static inline int test_and_clear_bit(int nr, volatile void *addr)
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{
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int oldval;
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__asm__ __volatile__ (
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" {R10 = %1; R11 = asr(%2,#5); }\n"
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" {R10 += asl(R11,#2); R11 = and(%2,#0x1f)}\n"
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"1: R12 = memw_locked(R10);\n"
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" { P0 = tstbit(R12,R11); R12 = clrbit(R12,R11); }\n"
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" memw_locked(R10,P1) = R12;\n"
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" {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n"
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: "=&r" (oldval)
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: "r" (addr), "r" (nr)
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: "r10", "r11", "r12", "p0", "p1", "memory"
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);
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return oldval;
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}
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/**
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* test_and_set_bit - set a bit and return its old value
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* @nr: bit number to set
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* @addr: pointer to memory
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*/
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static inline int test_and_set_bit(int nr, volatile void *addr)
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{
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int oldval;
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__asm__ __volatile__ (
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" {R10 = %1; R11 = asr(%2,#5); }\n"
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" {R10 += asl(R11,#2); R11 = and(%2,#0x1f)}\n"
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"1: R12 = memw_locked(R10);\n"
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" { P0 = tstbit(R12,R11); R12 = setbit(R12,R11); }\n"
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" memw_locked(R10,P1) = R12;\n"
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" {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n"
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: "=&r" (oldval)
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: "r" (addr), "r" (nr)
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: "r10", "r11", "r12", "p0", "p1", "memory"
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);
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return oldval;
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}
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/**
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* test_and_change_bit - toggle a bit and return its old value
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* @nr: bit number to set
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* @addr: pointer to memory
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*/
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static inline int test_and_change_bit(int nr, volatile void *addr)
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{
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int oldval;
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__asm__ __volatile__ (
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" {R10 = %1; R11 = asr(%2,#5); }\n"
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" {R10 += asl(R11,#2); R11 = and(%2,#0x1f)}\n"
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"1: R12 = memw_locked(R10);\n"
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" { P0 = tstbit(R12,R11); R12 = togglebit(R12,R11); }\n"
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" memw_locked(R10,P1) = R12;\n"
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" {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n"
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: "=&r" (oldval)
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: "r" (addr), "r" (nr)
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: "r10", "r11", "r12", "p0", "p1", "memory"
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);
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return oldval;
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}
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/*
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* Atomic, but doesn't care about the return value.
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* Rewrite later to save a cycle or two.
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*/
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static inline void clear_bit(int nr, volatile void *addr)
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{
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test_and_clear_bit(nr, addr);
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}
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static inline void set_bit(int nr, volatile void *addr)
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{
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test_and_set_bit(nr, addr);
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}
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static inline void change_bit(int nr, volatile void *addr)
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{
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test_and_change_bit(nr, addr);
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}
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/*
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* These are allowed to be non-atomic. In fact the generic flavors are
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* in non-atomic.h. Would it be better to use intrinsics for this?
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*
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* OK, writes in our architecture do not invalidate LL/SC, so this has to
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* be atomic, particularly for things like slab_lock and slab_unlock.
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*
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*/
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static __always_inline void
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arch___clear_bit(unsigned long nr, volatile unsigned long *addr)
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{
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test_and_clear_bit(nr, addr);
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}
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static __always_inline void
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arch___set_bit(unsigned long nr, volatile unsigned long *addr)
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{
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test_and_set_bit(nr, addr);
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}
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static __always_inline void
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arch___change_bit(unsigned long nr, volatile unsigned long *addr)
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{
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test_and_change_bit(nr, addr);
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}
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/* Apparently, at least some of these are allowed to be non-atomic */
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static __always_inline bool
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arch___test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
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{
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return test_and_clear_bit(nr, addr);
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}
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static __always_inline bool
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arch___test_and_set_bit(unsigned long nr, volatile unsigned long *addr)
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{
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return test_and_set_bit(nr, addr);
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}
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static __always_inline bool
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arch___test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
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{
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return test_and_change_bit(nr, addr);
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}
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static __always_inline bool
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arch_test_bit(unsigned long nr, const volatile unsigned long *addr)
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{
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int retval;
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asm volatile(
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"{P0 = tstbit(%1,%2); if (P0.new) %0 = #1; if (!P0.new) %0 = #0;}\n"
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: "=&r" (retval)
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: "r" (addr[BIT_WORD(nr)]), "r" (nr % BITS_PER_LONG)
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: "p0"
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);
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return retval;
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}
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/*
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* ffz - find first zero in word.
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* @word: The word to search
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*
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* Undefined if no zero exists, so code should check against ~0UL first.
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*/
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static inline long ffz(int x)
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{
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int r;
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asm("%0 = ct1(%1);\n"
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: "=&r" (r)
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: "r" (x));
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return r;
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}
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/*
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* fls - find last (most-significant) bit set
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* @x: the word to search
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*
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* This is defined the same way as ffs.
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* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
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*/
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static inline int fls(unsigned int x)
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{
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int r;
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asm("{ %0 = cl0(%1);}\n"
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"%0 = sub(#32,%0);\n"
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: "=&r" (r)
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: "r" (x)
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: "p0");
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return r;
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}
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/*
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* ffs - find first bit set
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* @x: the word to search
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*
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* This is defined the same way as
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* the libc and compiler builtin ffs routines, therefore
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* differs in spirit from the above ffz (man ffs).
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*/
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static inline int ffs(int x)
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{
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int r;
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asm("{ P0 = cmp.eq(%1,#0); %0 = ct0(%1);}\n"
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"{ if (P0) %0 = #0; if (!P0) %0 = add(%0,#1);}\n"
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: "=&r" (r)
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: "r" (x)
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: "p0");
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return r;
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}
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/*
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* __ffs - find first bit in word.
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* @word: The word to search
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*
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* Undefined if no bit exists, so code should check against 0 first.
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*
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* bits_per_long assumed to be 32
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* numbering starts at 0 I think (instead of 1 like ffs)
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*/
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static inline unsigned long __ffs(unsigned long word)
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{
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int num;
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asm("%0 = ct0(%1);\n"
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: "=&r" (num)
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: "r" (word));
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return num;
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}
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/*
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* __fls - find last (most-significant) set bit in a long word
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* @word: the word to search
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*
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* Undefined if no set bit exists, so code should check against 0 first.
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* bits_per_long assumed to be 32
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*/
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static inline unsigned long __fls(unsigned long word)
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{
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int num;
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asm("%0 = cl0(%1);\n"
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"%0 = sub(#31,%0);\n"
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: "=&r" (num)
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: "r" (word));
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return num;
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}
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#include <asm-generic/bitops/lock.h>
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#include <asm-generic/bitops/non-instrumented-non-atomic.h>
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#include <asm-generic/bitops/fls64.h>
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#include <asm-generic/bitops/sched.h>
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#include <asm-generic/bitops/hweight.h>
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#include <asm-generic/bitops/le.h>
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#include <asm-generic/bitops/ext2-atomic.h>
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#endif /* __KERNEL__ */
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#endif
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