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0e862838f2
Currently, there is a mess with the prototypes of the non-atomic bitops across the different architectures: ret bool, int, unsigned long nr int, long, unsigned int, unsigned long addr volatile unsigned long *, volatile void * Thankfully, it doesn't provoke any bugs, but can sometimes make the compiler angry when it's not handy at all. Adjust all the prototypes to the following standard: ret bool retval can be only 0 or 1 nr unsigned long native; signed makes no sense addr volatile unsigned long * bitmaps are arrays of ulongs Next, some architectures don't define 'arch_' versions as they don't support instrumentation, others do. To make sure there is always the same set of callables present and to ease any potential future changes, make them all follow the rule: * architecture-specific files define only 'arch_' versions; * non-prefixed versions can be defined only in asm-generic files; and place the non-prefixed definitions into a new file in asm-generic to be included by non-instrumented architectures. Finally, add some static assertions in order to prevent people from making a mess in this room again. I also used the %__always_inline attribute consistently, so that they always get resolved to the actual operations. Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Alexander Lobakin <alexandr.lobakin@intel.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Yury Norov <yury.norov@gmail.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Yury Norov <yury.norov@gmail.com>
151 lines
4 KiB
C
151 lines
4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_SH_BITOPS_OP32_H
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#define __ASM_SH_BITOPS_OP32_H
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#include <linux/bits.h>
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/*
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* The bit modifying instructions on SH-2A are only capable of working
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* with a 3-bit immediate, which signifies the shift position for the bit
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* being worked on.
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*/
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#if defined(__BIG_ENDIAN)
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#define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7)
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#define BYTE_NUMBER(nr) ((nr ^ BITOP_LE_SWIZZLE) / BITS_PER_BYTE)
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#define BYTE_OFFSET(nr) ((nr ^ BITOP_LE_SWIZZLE) % BITS_PER_BYTE)
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#else
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#define BYTE_NUMBER(nr) ((nr) / BITS_PER_BYTE)
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#define BYTE_OFFSET(nr) ((nr) % BITS_PER_BYTE)
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#endif
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static __always_inline void
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arch___set_bit(unsigned long nr, volatile unsigned long *addr)
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{
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if (__builtin_constant_p(nr)) {
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__asm__ __volatile__ (
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"bset.b %1, @(%O2,%0) ! __set_bit\n\t"
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: "+r" (addr)
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: "i" (BYTE_OFFSET(nr)), "i" (BYTE_NUMBER(nr))
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: "t", "memory"
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);
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} else {
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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*p |= mask;
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}
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}
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static __always_inline void
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arch___clear_bit(unsigned long nr, volatile unsigned long *addr)
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{
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if (__builtin_constant_p(nr)) {
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__asm__ __volatile__ (
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"bclr.b %1, @(%O2,%0) ! __clear_bit\n\t"
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: "+r" (addr)
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: "i" (BYTE_OFFSET(nr)),
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"i" (BYTE_NUMBER(nr))
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: "t", "memory"
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);
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} else {
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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*p &= ~mask;
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}
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}
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/**
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* arch___change_bit - Toggle a bit in memory
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* @nr: the bit to change
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* @addr: the address to start counting from
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*
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* Unlike change_bit(), this function is non-atomic and may be reordered.
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* If it's called on the same region of memory simultaneously, the effect
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* may be that only one operation succeeds.
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*/
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static __always_inline void
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arch___change_bit(unsigned long nr, volatile unsigned long *addr)
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{
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if (__builtin_constant_p(nr)) {
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__asm__ __volatile__ (
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"bxor.b %1, @(%O2,%0) ! __change_bit\n\t"
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: "+r" (addr)
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: "i" (BYTE_OFFSET(nr)),
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"i" (BYTE_NUMBER(nr))
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: "t", "memory"
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);
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} else {
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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*p ^= mask;
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}
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}
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/**
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* arch___test_and_set_bit - Set a bit and return its old value
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* @nr: Bit to set
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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static __always_inline bool
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arch___test_and_set_bit(unsigned long nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old = *p;
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*p = old | mask;
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return (old & mask) != 0;
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}
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/**
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* arch___test_and_clear_bit - Clear a bit and return its old value
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* @nr: Bit to clear
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* @addr: Address to count from
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*
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* This operation is non-atomic and can be reordered.
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* If two examples of this operation race, one can appear to succeed
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* but actually fail. You must protect multiple accesses with a lock.
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*/
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static __always_inline bool
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arch___test_and_clear_bit(unsigned long nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old = *p;
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*p = old & ~mask;
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return (old & mask) != 0;
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}
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/* WARNING: non atomic and it can be reordered! */
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static __always_inline bool
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arch___test_and_change_bit(unsigned long nr, volatile unsigned long *addr)
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{
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unsigned long mask = BIT_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
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unsigned long old = *p;
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*p = old ^ mask;
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return (old & mask) != 0;
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}
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/**
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* arch_test_bit - Determine whether a bit is set
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* @nr: bit number to test
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* @addr: Address to start counting from
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*/
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static __always_inline bool
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arch_test_bit(unsigned long nr, const volatile unsigned long *addr)
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{
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return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
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}
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#include <asm-generic/bitops/non-instrumented-non-atomic.h>
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#endif /* __ASM_SH_BITOPS_OP32_H */
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