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ad5b353240
Currently, an SEV-ES guest is terminated if the validation of the VMGEXIT
exit code or exit parameters fails.
The VMGEXIT instruction can be issued from userspace, even though
userspace (likely) can't update the GHCB. To prevent userspace from being
able to kill the guest, return an error through the GHCB when validation
fails rather than terminating the guest. For cases where the GHCB can't be
updated (e.g. the GHCB can't be mapped, etc.), just return back to the
guest.
The new error codes are documented in the lasest update to the GHCB
specification.
Fixes: 291bd20d5d ("KVM: SVM: Add initial support for a VMGEXIT VMEXIT")
Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com>
Message-Id: <b57280b5562893e2616257ac9c2d4525a9aeeb42.1638471124.git.thomas.lendacky@amd.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
87 lines
3 KiB
C
87 lines
3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* AMD SEV header common between the guest and the hypervisor.
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*
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* Author: Brijesh Singh <brijesh.singh@amd.com>
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*/
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#ifndef __ASM_X86_SEV_COMMON_H
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#define __ASM_X86_SEV_COMMON_H
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#define GHCB_MSR_INFO_POS 0
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#define GHCB_DATA_LOW 12
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#define GHCB_MSR_INFO_MASK (BIT_ULL(GHCB_DATA_LOW) - 1)
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#define GHCB_DATA(v) \
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(((unsigned long)(v) & ~GHCB_MSR_INFO_MASK) >> GHCB_DATA_LOW)
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/* SEV Information Request/Response */
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#define GHCB_MSR_SEV_INFO_RESP 0x001
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#define GHCB_MSR_SEV_INFO_REQ 0x002
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#define GHCB_MSR_VER_MAX_POS 48
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#define GHCB_MSR_VER_MAX_MASK 0xffff
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#define GHCB_MSR_VER_MIN_POS 32
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#define GHCB_MSR_VER_MIN_MASK 0xffff
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#define GHCB_MSR_CBIT_POS 24
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#define GHCB_MSR_CBIT_MASK 0xff
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#define GHCB_MSR_SEV_INFO(_max, _min, _cbit) \
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((((_max) & GHCB_MSR_VER_MAX_MASK) << GHCB_MSR_VER_MAX_POS) | \
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(((_min) & GHCB_MSR_VER_MIN_MASK) << GHCB_MSR_VER_MIN_POS) | \
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(((_cbit) & GHCB_MSR_CBIT_MASK) << GHCB_MSR_CBIT_POS) | \
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GHCB_MSR_SEV_INFO_RESP)
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#define GHCB_MSR_INFO(v) ((v) & 0xfffUL)
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#define GHCB_MSR_PROTO_MAX(v) (((v) >> GHCB_MSR_VER_MAX_POS) & GHCB_MSR_VER_MAX_MASK)
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#define GHCB_MSR_PROTO_MIN(v) (((v) >> GHCB_MSR_VER_MIN_POS) & GHCB_MSR_VER_MIN_MASK)
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/* CPUID Request/Response */
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#define GHCB_MSR_CPUID_REQ 0x004
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#define GHCB_MSR_CPUID_RESP 0x005
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#define GHCB_MSR_CPUID_FUNC_POS 32
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#define GHCB_MSR_CPUID_FUNC_MASK 0xffffffff
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#define GHCB_MSR_CPUID_VALUE_POS 32
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#define GHCB_MSR_CPUID_VALUE_MASK 0xffffffff
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#define GHCB_MSR_CPUID_REG_POS 30
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#define GHCB_MSR_CPUID_REG_MASK 0x3
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#define GHCB_CPUID_REQ_EAX 0
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#define GHCB_CPUID_REQ_EBX 1
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#define GHCB_CPUID_REQ_ECX 2
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#define GHCB_CPUID_REQ_EDX 3
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#define GHCB_CPUID_REQ(fn, reg) \
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(GHCB_MSR_CPUID_REQ | \
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(((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \
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(((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS))
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/* AP Reset Hold */
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#define GHCB_MSR_AP_RESET_HOLD_REQ 0x006
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#define GHCB_MSR_AP_RESET_HOLD_RESP 0x007
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/* GHCB Hypervisor Feature Request/Response */
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#define GHCB_MSR_HV_FT_REQ 0x080
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#define GHCB_MSR_HV_FT_RESP 0x081
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#define GHCB_MSR_TERM_REQ 0x100
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#define GHCB_MSR_TERM_REASON_SET_POS 12
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#define GHCB_MSR_TERM_REASON_SET_MASK 0xf
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#define GHCB_MSR_TERM_REASON_POS 16
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#define GHCB_MSR_TERM_REASON_MASK 0xff
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#define GHCB_SEV_TERM_REASON(reason_set, reason_val) \
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(((((u64)reason_set) & GHCB_MSR_TERM_REASON_SET_MASK) << GHCB_MSR_TERM_REASON_SET_POS) | \
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((((u64)reason_val) & GHCB_MSR_TERM_REASON_MASK) << GHCB_MSR_TERM_REASON_POS))
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#define GHCB_SEV_ES_REASON_GENERAL_REQUEST 0
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#define GHCB_SEV_ES_REASON_PROTOCOL_UNSUPPORTED 1
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#define GHCB_RESP_CODE(v) ((v) & GHCB_MSR_INFO_MASK)
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/*
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* Error codes related to GHCB input that can be communicated back to the guest
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* by setting the lower 32-bits of the GHCB SW_EXITINFO1 field to 2.
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*/
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#define GHCB_ERR_NOT_REGISTERED 1
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#define GHCB_ERR_INVALID_USAGE 2
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#define GHCB_ERR_INVALID_SCRATCH_AREA 3
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#define GHCB_ERR_MISSING_INPUT 4
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#define GHCB_ERR_INVALID_INPUT 5
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#define GHCB_ERR_INVALID_EVENT 6
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#endif
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