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https://gitee.com/bianbu-linux/linux-6.6
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a35707c3d8
Some current cpus based on T-Head cores implement memory-types way different than described in the svpbmt spec even going so far as using PTE bits marked as reserved. Add the T-Head vendor-id and necessary errata code to replace the affected instructions. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220511192921.2223629-13-heiko@sntech.de Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
98 lines
2.7 KiB
C
98 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2021 Sifive.
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*/
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#ifndef ASM_ERRATA_LIST_H
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#define ASM_ERRATA_LIST_H
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#include <asm/alternative.h>
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#include <asm/vendorid_list.h>
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#ifdef CONFIG_ERRATA_SIFIVE
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#define ERRATA_SIFIVE_CIP_453 0
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#define ERRATA_SIFIVE_CIP_1200 1
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#define ERRATA_SIFIVE_NUMBER 2
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#endif
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#ifdef CONFIG_ERRATA_THEAD
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#define ERRATA_THEAD_PBMT 0
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#define ERRATA_THEAD_NUMBER 1
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#endif
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#define CPUFEATURE_SVPBMT 0
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#define CPUFEATURE_NUMBER 1
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#ifdef __ASSEMBLY__
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#define ALT_INSN_FAULT(x) \
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ALTERNATIVE(__stringify(RISCV_PTR do_trap_insn_fault), \
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__stringify(RISCV_PTR sifive_cip_453_insn_fault_trp), \
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SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \
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CONFIG_ERRATA_SIFIVE_CIP_453)
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#define ALT_PAGE_FAULT(x) \
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ALTERNATIVE(__stringify(RISCV_PTR do_page_fault), \
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__stringify(RISCV_PTR sifive_cip_453_page_fault_trp), \
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SIFIVE_VENDOR_ID, ERRATA_SIFIVE_CIP_453, \
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CONFIG_ERRATA_SIFIVE_CIP_453)
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#else /* !__ASSEMBLY__ */
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#define ALT_FLUSH_TLB_PAGE(x) \
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asm(ALTERNATIVE("sfence.vma %0", "sfence.vma", SIFIVE_VENDOR_ID, \
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ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200) \
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: : "r" (addr) : "memory")
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/*
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* _val is marked as "will be overwritten", so need to set it to 0
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* in the default case.
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*/
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#define ALT_SVPBMT_SHIFT 61
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#define ALT_THEAD_PBMT_SHIFT 59
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#define ALT_SVPBMT(_val, prot) \
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asm(ALTERNATIVE_2("li %0, 0\t\nnop", \
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"li %0, %1\t\nslli %0,%0,%3", 0, \
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CPUFEATURE_SVPBMT, CONFIG_RISCV_ISA_SVPBMT, \
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"li %0, %2\t\nslli %0,%0,%4", THEAD_VENDOR_ID, \
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ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \
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: "=r"(_val) \
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: "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \
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"I"(prot##_THEAD >> ALT_THEAD_PBMT_SHIFT), \
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"I"(ALT_SVPBMT_SHIFT), \
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"I"(ALT_THEAD_PBMT_SHIFT))
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#ifdef CONFIG_ERRATA_THEAD_PBMT
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/*
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* IO/NOCACHE memory types are handled together with svpbmt,
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* so on T-Head chips, check if no other memory type is set,
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* and set the non-0 PMA type if applicable.
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*/
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#define ALT_THEAD_PMA(_val) \
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asm volatile(ALTERNATIVE( \
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"nop\n\t" \
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"nop\n\t" \
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"nop\n\t" \
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"nop\n\t" \
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"nop\n\t" \
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"nop\n\t" \
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"nop", \
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"li t3, %2\n\t" \
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"slli t3, t3, %4\n\t" \
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"and t3, %0, t3\n\t" \
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"bne t3, zero, 2f\n\t" \
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"li t3, %3\n\t" \
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"slli t3, t3, %4\n\t" \
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"or %0, %0, t3\n\t" \
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"2:", THEAD_VENDOR_ID, \
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ERRATA_THEAD_PBMT, CONFIG_ERRATA_THEAD_PBMT) \
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: "+r"(_val) \
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: "0"(_val), \
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"I"(_PAGE_MTMASK_THEAD >> ALT_THEAD_PBMT_SHIFT), \
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"I"(_PAGE_PMA_THEAD >> ALT_THEAD_PBMT_SHIFT), \
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"I"(ALT_THEAD_PBMT_SHIFT))
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#else
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#define ALT_THEAD_PMA(_val)
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#endif
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#endif /* __ASSEMBLY__ */
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#endif
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