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On OcteonTX2 platform CPT instruction enqueue and NIX packet send are only possible via LMTST operations which uses LDEOR instruction. This patch moves lmt flush function from OcteonTX2 nic driver to include/linux/soc since it will be used by OcteonTX2 CPT and NIC driver for LMTST. Signed-off-by: Suheil Chandran <schandran@marvell.com> Signed-off-by: Srujana Challa <schalla@marvell.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
29 lines
870 B
C
29 lines
870 B
C
/* SPDX-License-Identifier: GPL-2.0-only
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* Copyright (C) 2020 Marvell.
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*/
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#ifndef __SOC_OTX2_ASM_H
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#define __SOC_OTX2_ASM_H
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#if defined(CONFIG_ARM64)
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/*
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* otx2_lmt_flush is used for LMT store operation.
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* On octeontx2 platform CPT instruction enqueue and
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* NIX packet send are only possible via LMTST
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* operations and it uses LDEOR instruction targeting
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* the coprocessor address.
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*/
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#define otx2_lmt_flush(ioaddr) \
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({ \
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u64 result = 0; \
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__asm__ volatile(".cpu generic+lse\n" \
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"ldeor xzr, %x[rf], [%[rs]]" \
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: [rf]"=r" (result) \
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: [rs]"r" (ioaddr)); \
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(result); \
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})
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#else
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#define otx2_lmt_flush(ioaddr) ({ 0; })
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#endif
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#endif /* __SOC_OTX2_ASM_H */
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