mirror of
https://gitee.com/bianbu-linux/linux-6.6
synced 2025-07-24 01:54:03 -04:00
175c241288
If a user schedules a Gate Control List (GCL) to close one of
the QBV gates while also transmitting a packet to that closed gate,
TX Hang will be happen. HW would not drop any packet when the gate
is closed and keep queuing up in HW TX FIFO until the gate is re-opened.
This patch implements the solution to drop the packet for the closed
gate.
This patch will also reset the adapter to perform SW initialization
for each 1st Gate Control List (GCL) to avoid hang.
This is due to the HW design, where changing to TSN transmit mode
requires SW initialization. Intel Discrete I225/6 transmit mode
cannot be changed when in dynamic mode according to Software User
Manual Section 7.5.2.1. Subsequent Gate Control List (GCL) operations
will proceed without a reset, as they already are in TSN Mode.
Step to reproduce:
DUT:
1) Configure GCL List with certain gate close.
BASE=$(date +%s%N)
tc qdisc replace dev $IFACE parent root handle 100 taprio \
num_tc 4 \
map 0 1 2 3 3 3 3 3 3 3 3 3 3 3 3 3 \
queues 1@0 1@1 1@2 1@3 \
base-time $BASE \
sched-entry S 0x8 500000 \
sched-entry S 0x4 500000 \
flags 0x2
2) Transmit the packet to closed gate. You may use udp_tai
application to transmit UDP packet to any of the closed gate.
./udp_tai -i <interface> -P 100000 -p 90 -c 1 -t <0/1> -u 30004
Fixes: ec50a9d437 ("igc: Add support for taprio offloading")
Co-developed-by: Tan Tee Min <tee.min.tan@linux.intel.com>
Signed-off-by: Tan Tee Min <tee.min.tan@linux.intel.com>
Tested-by: Chwee Lin Choong <chwee.lin.choong@intel.com>
Signed-off-by: Muhammad Husaini Zulkifli <muhammad.husaini.zulkifli@intel.com>
Tested-by: Naama Meir <naamax.meir@linux.intel.com>
Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
330 lines
8.2 KiB
C
330 lines
8.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/* Copyright (c) 2019 Intel Corporation */
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#include "igc.h"
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#include "igc_hw.h"
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#include "igc_tsn.h"
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static bool is_any_launchtime(struct igc_adapter *adapter)
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{
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int i;
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for (i = 0; i < adapter->num_tx_queues; i++) {
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struct igc_ring *ring = adapter->tx_ring[i];
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if (ring->launchtime_enable)
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return true;
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}
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return false;
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}
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static bool is_cbs_enabled(struct igc_adapter *adapter)
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{
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int i;
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for (i = 0; i < adapter->num_tx_queues; i++) {
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struct igc_ring *ring = adapter->tx_ring[i];
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if (ring->cbs_enable)
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return true;
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}
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return false;
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}
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static unsigned int igc_tsn_new_flags(struct igc_adapter *adapter)
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{
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unsigned int new_flags = adapter->flags & ~IGC_FLAG_TSN_ANY_ENABLED;
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if (adapter->qbv_enable)
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new_flags |= IGC_FLAG_TSN_QBV_ENABLED;
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if (is_any_launchtime(adapter))
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new_flags |= IGC_FLAG_TSN_QBV_ENABLED;
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if (is_cbs_enabled(adapter))
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new_flags |= IGC_FLAG_TSN_QAV_ENABLED;
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return new_flags;
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}
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void igc_tsn_adjust_txtime_offset(struct igc_adapter *adapter)
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{
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struct igc_hw *hw = &adapter->hw;
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u16 txoffset;
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if (!is_any_launchtime(adapter))
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return;
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switch (adapter->link_speed) {
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case SPEED_10:
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txoffset = IGC_TXOFFSET_SPEED_10;
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break;
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case SPEED_100:
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txoffset = IGC_TXOFFSET_SPEED_100;
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break;
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case SPEED_1000:
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txoffset = IGC_TXOFFSET_SPEED_1000;
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break;
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case SPEED_2500:
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txoffset = IGC_TXOFFSET_SPEED_2500;
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break;
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default:
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txoffset = 0;
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break;
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}
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wr32(IGC_GTXOFFSET, txoffset);
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}
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/* Returns the TSN specific registers to their default values after
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* the adapter is reset.
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*/
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static int igc_tsn_disable_offload(struct igc_adapter *adapter)
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{
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struct igc_hw *hw = &adapter->hw;
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u32 tqavctrl;
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int i;
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wr32(IGC_GTXOFFSET, 0);
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wr32(IGC_TXPBS, I225_TXPBSIZE_DEFAULT);
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wr32(IGC_DTXMXPKTSZ, IGC_DTXMXPKTSZ_DEFAULT);
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tqavctrl = rd32(IGC_TQAVCTRL);
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tqavctrl &= ~(IGC_TQAVCTRL_TRANSMIT_MODE_TSN |
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IGC_TQAVCTRL_ENHANCED_QAV | IGC_TQAVCTRL_FUTSCDDIS);
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wr32(IGC_TQAVCTRL, tqavctrl);
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for (i = 0; i < adapter->num_tx_queues; i++) {
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wr32(IGC_TXQCTL(i), 0);
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wr32(IGC_STQT(i), 0);
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wr32(IGC_ENDQT(i), NSEC_PER_SEC);
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}
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wr32(IGC_QBVCYCLET_S, 0);
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wr32(IGC_QBVCYCLET, NSEC_PER_SEC);
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adapter->flags &= ~IGC_FLAG_TSN_QBV_ENABLED;
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return 0;
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}
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static int igc_tsn_enable_offload(struct igc_adapter *adapter)
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{
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struct igc_hw *hw = &adapter->hw;
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u32 tqavctrl, baset_l, baset_h;
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u32 sec, nsec, cycle;
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ktime_t base_time, systim;
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int i;
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wr32(IGC_TSAUXC, 0);
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wr32(IGC_DTXMXPKTSZ, IGC_DTXMXPKTSZ_TSN);
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wr32(IGC_TXPBS, IGC_TXPBSIZE_TSN);
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for (i = 0; i < adapter->num_tx_queues; i++) {
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struct igc_ring *ring = adapter->tx_ring[i];
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u32 txqctl = 0;
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u16 cbs_value;
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u32 tqavcc;
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wr32(IGC_STQT(i), ring->start_time);
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wr32(IGC_ENDQT(i), ring->end_time);
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txqctl |= IGC_TXQCTL_STRICT_CYCLE |
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IGC_TXQCTL_STRICT_END;
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if (ring->launchtime_enable)
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txqctl |= IGC_TXQCTL_QUEUE_MODE_LAUNCHT;
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/* Skip configuring CBS for Q2 and Q3 */
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if (i > 1)
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goto skip_cbs;
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if (ring->cbs_enable) {
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if (i == 0)
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txqctl |= IGC_TXQCTL_QAV_SEL_CBS0;
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else
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txqctl |= IGC_TXQCTL_QAV_SEL_CBS1;
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/* According to i225 datasheet section 7.5.2.7, we
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* should set the 'idleSlope' field from TQAVCC
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* register following the equation:
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*
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* value = link-speed 0x7736 * BW * 0.2
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* ---------- * ----------------- (E1)
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* 100Mbps 2.5
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*
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* Note that 'link-speed' is in Mbps.
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*
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* 'BW' is the percentage bandwidth out of full
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* link speed which can be found with the
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* following equation. Note that idleSlope here
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* is the parameter from this function
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* which is in kbps.
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*
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* BW = idleSlope
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* ----------------- (E2)
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* link-speed * 1000
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*
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* That said, we can come up with a generic
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* equation to calculate the value we should set
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* it TQAVCC register by replacing 'BW' in E1 by E2.
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* The resulting equation is:
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*
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* value = link-speed * 0x7736 * idleSlope * 0.2
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* ------------------------------------- (E3)
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* 100 * 2.5 * link-speed * 1000
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*
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* 'link-speed' is present in both sides of the
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* fraction so it is canceled out. The final
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* equation is the following:
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*
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* value = idleSlope * 61036
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* ----------------- (E4)
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* 2500000
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*
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* NOTE: For i225, given the above, we can see
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* that idleslope is represented in
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* 40.959433 kbps units by the value at
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* the TQAVCC register (2.5Gbps / 61036),
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* which reduces the granularity for
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* idleslope increments.
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*
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* In i225 controller, the sendSlope and loCredit
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* parameters from CBS are not configurable
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* by software so we don't do any
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* 'controller configuration' in respect to
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* these parameters.
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*/
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cbs_value = DIV_ROUND_UP_ULL(ring->idleslope
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* 61036ULL, 2500000);
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tqavcc = rd32(IGC_TQAVCC(i));
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tqavcc &= ~IGC_TQAVCC_IDLESLOPE_MASK;
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tqavcc |= cbs_value | IGC_TQAVCC_KEEP_CREDITS;
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wr32(IGC_TQAVCC(i), tqavcc);
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wr32(IGC_TQAVHC(i),
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0x80000000 + ring->hicredit * 0x7735);
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} else {
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/* Disable any CBS for the queue */
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txqctl &= ~(IGC_TXQCTL_QAV_SEL_MASK);
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/* Set idleSlope to zero. */
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tqavcc = rd32(IGC_TQAVCC(i));
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tqavcc &= ~(IGC_TQAVCC_IDLESLOPE_MASK |
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IGC_TQAVCC_KEEP_CREDITS);
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wr32(IGC_TQAVCC(i), tqavcc);
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/* Set hiCredit to zero. */
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wr32(IGC_TQAVHC(i), 0);
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}
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skip_cbs:
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wr32(IGC_TXQCTL(i), txqctl);
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}
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tqavctrl = rd32(IGC_TQAVCTRL) & ~IGC_TQAVCTRL_FUTSCDDIS;
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tqavctrl |= IGC_TQAVCTRL_TRANSMIT_MODE_TSN | IGC_TQAVCTRL_ENHANCED_QAV;
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adapter->qbv_count++;
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cycle = adapter->cycle_time;
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base_time = adapter->base_time;
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nsec = rd32(IGC_SYSTIML);
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sec = rd32(IGC_SYSTIMH);
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systim = ktime_set(sec, nsec);
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if (ktime_compare(systim, base_time) > 0) {
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s64 n = div64_s64(ktime_sub_ns(systim, base_time), cycle);
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base_time = ktime_add_ns(base_time, (n + 1) * cycle);
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/* Increase the counter if scheduling into the past while
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* Gate Control List (GCL) is running.
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*/
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if ((rd32(IGC_BASET_H) || rd32(IGC_BASET_L)) &&
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(adapter->tc_setup_type == TC_SETUP_QDISC_TAPRIO) &&
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(adapter->qbv_count > 1))
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adapter->qbv_config_change_errors++;
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} else {
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if (igc_is_device_id_i226(hw)) {
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ktime_t adjust_time, expires_time;
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/* According to datasheet section 7.5.2.9.3.3, FutScdDis bit
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* has to be configured before the cycle time and base time.
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* Tx won't hang if a GCL is already running,
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* so in this case we don't need to set FutScdDis.
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*/
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if (!(rd32(IGC_BASET_H) || rd32(IGC_BASET_L)))
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tqavctrl |= IGC_TQAVCTRL_FUTSCDDIS;
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nsec = rd32(IGC_SYSTIML);
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sec = rd32(IGC_SYSTIMH);
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systim = ktime_set(sec, nsec);
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adjust_time = adapter->base_time;
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expires_time = ktime_sub_ns(adjust_time, systim);
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hrtimer_start(&adapter->hrtimer, expires_time, HRTIMER_MODE_REL);
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}
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}
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wr32(IGC_TQAVCTRL, tqavctrl);
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wr32(IGC_QBVCYCLET_S, cycle);
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wr32(IGC_QBVCYCLET, cycle);
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baset_h = div_s64_rem(base_time, NSEC_PER_SEC, &baset_l);
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wr32(IGC_BASET_H, baset_h);
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/* In i226, Future base time is only supported when FutScdDis bit
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* is enabled and only active for re-configuration.
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* In this case, initialize the base time with zero to create
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* "re-configuration" scenario then only set the desired base time.
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*/
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if (tqavctrl & IGC_TQAVCTRL_FUTSCDDIS)
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wr32(IGC_BASET_L, 0);
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wr32(IGC_BASET_L, baset_l);
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return 0;
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}
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int igc_tsn_reset(struct igc_adapter *adapter)
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{
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unsigned int new_flags;
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int err = 0;
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new_flags = igc_tsn_new_flags(adapter);
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if (!(new_flags & IGC_FLAG_TSN_ANY_ENABLED))
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return igc_tsn_disable_offload(adapter);
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err = igc_tsn_enable_offload(adapter);
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if (err < 0)
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return err;
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adapter->flags = new_flags;
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return err;
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}
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int igc_tsn_offload_apply(struct igc_adapter *adapter)
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{
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struct igc_hw *hw = &adapter->hw;
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/* Per I225/6 HW Design Section 7.5.2.1, transmit mode
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* cannot be changed dynamically. Require reset the adapter.
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*/
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if (netif_running(adapter->netdev) &&
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(igc_is_device_id_i225(hw) || !adapter->qbv_count)) {
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schedule_work(&adapter->reset_task);
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return 0;
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}
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igc_tsn_reset(adapter);
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return 0;
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}
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