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https://gitee.com/bianbu-linux/linux-6.6
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fa7e843a90
MT2712 add "set/clear" bus control register to each control register set instead of providing only one "enable" control register, we could avoid the read-modify-write racing by declaring "bus_prot_reg_update" as "false" in scp_soc_data or declaring as "true" to use the legacy update method. By improving the mtk-infracfg bus protection implementation to support set/clear bus protection control method by IC configuration. Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
35 lines
1.4 KiB
C
35 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __SOC_MEDIATEK_INFRACFG_H
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#define __SOC_MEDIATEK_INFRACFG_H
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#define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0)
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#define MT8173_TOP_AXI_PROT_EN_MM_M0 BIT(1)
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#define MT8173_TOP_AXI_PROT_EN_MM_M1 BIT(2)
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#define MT8173_TOP_AXI_PROT_EN_MMAPB_S BIT(6)
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#define MT8173_TOP_AXI_PROT_EN_L2C_M2 BIT(9)
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#define MT8173_TOP_AXI_PROT_EN_L2SS_SMI BIT(11)
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#define MT8173_TOP_AXI_PROT_EN_L2SS_ADD BIT(12)
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#define MT8173_TOP_AXI_PROT_EN_CCI_M2 BIT(13)
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#define MT8173_TOP_AXI_PROT_EN_MFG_S BIT(14)
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#define MT8173_TOP_AXI_PROT_EN_PERI_M0 BIT(15)
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#define MT8173_TOP_AXI_PROT_EN_PERI_M1 BIT(16)
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#define MT8173_TOP_AXI_PROT_EN_DEBUGSYS BIT(17)
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#define MT8173_TOP_AXI_PROT_EN_CQ_DMA BIT(18)
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#define MT8173_TOP_AXI_PROT_EN_GCPU BIT(19)
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#define MT8173_TOP_AXI_PROT_EN_IOMMU BIT(20)
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#define MT8173_TOP_AXI_PROT_EN_MFG_M0 BIT(21)
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#define MT8173_TOP_AXI_PROT_EN_MFG_M1 BIT(22)
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#define MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT BIT(23)
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#define MT7622_TOP_AXI_PROT_EN_ETHSYS (BIT(3) | BIT(17))
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#define MT7622_TOP_AXI_PROT_EN_HIF0 (BIT(24) | BIT(25))
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#define MT7622_TOP_AXI_PROT_EN_HIF1 (BIT(26) | BIT(27) | \
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BIT(28))
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#define MT7622_TOP_AXI_PROT_EN_WB (BIT(2) | BIT(6) | \
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BIT(7) | BIT(8))
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int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
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bool reg_update);
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int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
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bool reg_update);
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#endif /* __SOC_MEDIATEK_INFRACFG_H */
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