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Why: Limit maximum clock speeds to DC mode limits for DC mode systems How: Store DC mode limits when individual clocks are initialized and cap the values when building the clock table Acked-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Austin Zheng <austin.zheng@amd.com> Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> |
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.. | ||
hw | ||
bw_fixed.h | ||
clock_source.h | ||
compressor.h | ||
core_status.h | ||
core_types.h | ||
custom_float.h | ||
dce_calcs.h | ||
dcn_calc_math.h | ||
dcn_calcs.h | ||
hw_sequencer.h | ||
hw_sequencer_private.h | ||
link.h | ||
link_enc_cfg.h | ||
link_hwss.h | ||
reg_helper.h | ||
resource.h | ||
vm_helper.h |