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https://gitee.com/bianbu-linux/linux-6.6
synced 2025-07-24 01:54:03 -04:00
34fb0e7034
Currently it is not detectable from within Linux when PCI instructions are retried because of a busy condition. Detecting such conditions and especially how long they lasted can however be quite useful in problem determination. This patch enables this by adding an s390dbf error log when a CC 2 is first encountered as well as after the retried instruction. Despite being unlikely it may be possible that these added debug messages drown out important other messages so allow setting the debug level in zpci_err_insn*() and set their level to 1 so they can be filtered out if need be. Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com> Reviewed-by: Pierre Morel <pmorel@linux.ibm.com> Signed-off-by: Niklas Schnelle <schnelle@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
441 lines
9.7 KiB
C
441 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* s390 specific pci instructions
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*
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* Copyright IBM Corp. 2013
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*/
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#include <linux/export.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/jump_label.h>
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#include <asm/asm-extable.h>
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#include <asm/facility.h>
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#include <asm/pci_insn.h>
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#include <asm/pci_debug.h>
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#include <asm/pci_io.h>
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#include <asm/processor.h>
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#define ZPCI_INSN_BUSY_DELAY 1 /* 1 microsecond */
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struct zpci_err_insn_data {
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u8 insn;
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u8 cc;
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u8 status;
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union {
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struct {
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u64 req;
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u64 offset;
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};
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struct {
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u64 addr;
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u64 len;
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};
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};
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} __packed;
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static inline void zpci_err_insn_req(int lvl, u8 insn, u8 cc, u8 status,
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u64 req, u64 offset)
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{
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struct zpci_err_insn_data data = {
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.insn = insn, .cc = cc, .status = status,
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.req = req, .offset = offset};
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zpci_err_hex_level(lvl, &data, sizeof(data));
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}
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static inline void zpci_err_insn_addr(int lvl, u8 insn, u8 cc, u8 status,
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u64 addr, u64 len)
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{
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struct zpci_err_insn_data data = {
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.insn = insn, .cc = cc, .status = status,
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.addr = addr, .len = len};
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zpci_err_hex_level(lvl, &data, sizeof(data));
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}
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/* Modify PCI Function Controls */
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static inline u8 __mpcifc(u64 req, struct zpci_fib *fib, u8 *status)
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{
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u8 cc;
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asm volatile (
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" .insn rxy,0xe300000000d0,%[req],%[fib]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [req] "+d" (req), [fib] "+Q" (*fib)
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: : "cc");
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*status = req >> 24 & 0xff;
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return cc;
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}
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u8 zpci_mod_fc(u64 req, struct zpci_fib *fib, u8 *status)
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{
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bool retried = false;
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u8 cc;
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do {
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cc = __mpcifc(req, fib, status);
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if (cc == 2) {
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msleep(ZPCI_INSN_BUSY_DELAY);
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if (!retried) {
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zpci_err_insn_req(1, 'M', cc, *status, req, 0);
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retried = true;
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}
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}
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} while (cc == 2);
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if (cc)
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zpci_err_insn_req(0, 'M', cc, *status, req, 0);
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else if (retried)
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zpci_err_insn_req(1, 'M', cc, *status, req, 0);
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return cc;
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}
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/* Refresh PCI Translations */
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static inline u8 __rpcit(u64 fn, u64 addr, u64 range, u8 *status)
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{
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union register_pair addr_range = {.even = addr, .odd = range};
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u8 cc;
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asm volatile (
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" .insn rre,0xb9d30000,%[fn],%[addr_range]\n"
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" ipm %[cc]\n"
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" srl %[cc],28\n"
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: [cc] "=d" (cc), [fn] "+d" (fn)
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: [addr_range] "d" (addr_range.pair)
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: "cc");
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*status = fn >> 24 & 0xff;
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return cc;
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}
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int zpci_refresh_trans(u64 fn, u64 addr, u64 range)
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{
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bool retried = false;
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u8 cc, status;
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do {
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cc = __rpcit(fn, addr, range, &status);
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if (cc == 2) {
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udelay(ZPCI_INSN_BUSY_DELAY);
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if (!retried) {
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zpci_err_insn_addr(1, 'R', cc, status, addr, range);
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retried = true;
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}
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}
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} while (cc == 2);
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if (cc)
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zpci_err_insn_addr(0, 'R', cc, status, addr, range);
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else if (retried)
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zpci_err_insn_addr(1, 'R', cc, status, addr, range);
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if (cc == 1 && (status == 4 || status == 16))
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return -ENOMEM;
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return (cc) ? -EIO : 0;
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}
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/* Set Interruption Controls */
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int __zpci_set_irq_ctrl(u16 ctl, u8 isc, union zpci_sic_iib *iib)
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{
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if (!test_facility(72))
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return -EIO;
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asm volatile(
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".insn rsy,0xeb00000000d1,%[ctl],%[isc],%[iib]\n"
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: : [ctl] "d" (ctl), [isc] "d" (isc << 27), [iib] "Q" (*iib));
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return 0;
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}
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/* PCI Load */
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static inline int ____pcilg(u64 *data, u64 req, u64 offset, u8 *status)
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{
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union register_pair req_off = {.even = req, .odd = offset};
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int cc = -ENXIO;
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u64 __data;
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asm volatile (
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" .insn rre,0xb9d20000,%[data],%[req_off]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [data] "=d" (__data),
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[req_off] "+&d" (req_off.pair) :: "cc");
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*status = req_off.even >> 24 & 0xff;
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*data = __data;
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return cc;
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}
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static inline int __pcilg(u64 *data, u64 req, u64 offset, u8 *status)
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{
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u64 __data;
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int cc;
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cc = ____pcilg(&__data, req, offset, status);
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if (!cc)
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*data = __data;
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return cc;
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}
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int __zpci_load(u64 *data, u64 req, u64 offset)
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{
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bool retried = false;
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u8 status;
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int cc;
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do {
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cc = __pcilg(data, req, offset, &status);
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if (cc == 2) {
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udelay(ZPCI_INSN_BUSY_DELAY);
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if (!retried) {
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zpci_err_insn_req(1, 'l', cc, status, req, offset);
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retried = true;
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}
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}
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} while (cc == 2);
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if (cc)
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zpci_err_insn_req(0, 'l', cc, status, req, offset);
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else if (retried)
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zpci_err_insn_req(1, 'l', cc, status, req, offset);
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return (cc > 0) ? -EIO : cc;
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}
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EXPORT_SYMBOL_GPL(__zpci_load);
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static inline int zpci_load_fh(u64 *data, const volatile void __iomem *addr,
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unsigned long len)
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{
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struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(addr)];
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u64 req = ZPCI_CREATE_REQ(READ_ONCE(entry->fh), entry->bar, len);
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return __zpci_load(data, req, ZPCI_OFFSET(addr));
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}
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static inline int __pcilg_mio(u64 *data, u64 ioaddr, u64 len, u8 *status)
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{
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union register_pair ioaddr_len = {.even = ioaddr, .odd = len};
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int cc = -ENXIO;
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u64 __data;
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asm volatile (
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" .insn rre,0xb9d60000,%[data],%[ioaddr_len]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [data] "=d" (__data),
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[ioaddr_len] "+&d" (ioaddr_len.pair) :: "cc");
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*status = ioaddr_len.odd >> 24 & 0xff;
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*data = __data;
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return cc;
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}
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int zpci_load(u64 *data, const volatile void __iomem *addr, unsigned long len)
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{
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u8 status;
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int cc;
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if (!static_branch_unlikely(&have_mio))
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return zpci_load_fh(data, addr, len);
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cc = __pcilg_mio(data, (__force u64) addr, len, &status);
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if (cc)
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zpci_err_insn_addr(0, 'L', cc, status, (__force u64) addr, len);
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return (cc > 0) ? -EIO : cc;
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}
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EXPORT_SYMBOL_GPL(zpci_load);
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/* PCI Store */
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static inline int __pcistg(u64 data, u64 req, u64 offset, u8 *status)
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{
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union register_pair req_off = {.even = req, .odd = offset};
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int cc = -ENXIO;
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asm volatile (
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" .insn rre,0xb9d00000,%[data],%[req_off]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [req_off] "+&d" (req_off.pair)
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: [data] "d" (data)
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: "cc");
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*status = req_off.even >> 24 & 0xff;
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return cc;
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}
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int __zpci_store(u64 data, u64 req, u64 offset)
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{
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bool retried = false;
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u8 status;
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int cc;
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do {
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cc = __pcistg(data, req, offset, &status);
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if (cc == 2) {
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udelay(ZPCI_INSN_BUSY_DELAY);
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if (!retried) {
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zpci_err_insn_req(1, 's', cc, status, req, offset);
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retried = true;
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}
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}
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} while (cc == 2);
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if (cc)
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zpci_err_insn_req(0, 's', cc, status, req, offset);
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else if (retried)
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zpci_err_insn_req(1, 's', cc, status, req, offset);
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return (cc > 0) ? -EIO : cc;
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}
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EXPORT_SYMBOL_GPL(__zpci_store);
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static inline int zpci_store_fh(const volatile void __iomem *addr, u64 data,
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unsigned long len)
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{
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struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(addr)];
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u64 req = ZPCI_CREATE_REQ(READ_ONCE(entry->fh), entry->bar, len);
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return __zpci_store(data, req, ZPCI_OFFSET(addr));
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}
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static inline int __pcistg_mio(u64 data, u64 ioaddr, u64 len, u8 *status)
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{
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union register_pair ioaddr_len = {.even = ioaddr, .odd = len};
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int cc = -ENXIO;
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asm volatile (
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" .insn rre,0xb9d40000,%[data],%[ioaddr_len]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [ioaddr_len] "+&d" (ioaddr_len.pair)
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: [data] "d" (data)
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: "cc", "memory");
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*status = ioaddr_len.odd >> 24 & 0xff;
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return cc;
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}
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int zpci_store(const volatile void __iomem *addr, u64 data, unsigned long len)
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{
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u8 status;
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int cc;
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if (!static_branch_unlikely(&have_mio))
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return zpci_store_fh(addr, data, len);
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cc = __pcistg_mio(data, (__force u64) addr, len, &status);
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if (cc)
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zpci_err_insn_addr(0, 'S', cc, status, (__force u64) addr, len);
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return (cc > 0) ? -EIO : cc;
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}
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EXPORT_SYMBOL_GPL(zpci_store);
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/* PCI Store Block */
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static inline int __pcistb(const u64 *data, u64 req, u64 offset, u8 *status)
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{
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int cc = -ENXIO;
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asm volatile (
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" .insn rsy,0xeb00000000d0,%[req],%[offset],%[data]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [req] "+d" (req)
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: [offset] "d" (offset), [data] "Q" (*data)
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: "cc");
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*status = req >> 24 & 0xff;
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return cc;
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}
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int __zpci_store_block(const u64 *data, u64 req, u64 offset)
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{
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bool retried = false;
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u8 status;
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int cc;
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do {
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cc = __pcistb(data, req, offset, &status);
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if (cc == 2) {
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udelay(ZPCI_INSN_BUSY_DELAY);
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if (!retried) {
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zpci_err_insn_req(0, 'b', cc, status, req, offset);
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retried = true;
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}
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}
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} while (cc == 2);
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if (cc)
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zpci_err_insn_req(0, 'b', cc, status, req, offset);
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else if (retried)
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zpci_err_insn_req(1, 'b', cc, status, req, offset);
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return (cc > 0) ? -EIO : cc;
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}
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EXPORT_SYMBOL_GPL(__zpci_store_block);
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static inline int zpci_write_block_fh(volatile void __iomem *dst,
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const void *src, unsigned long len)
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{
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struct zpci_iomap_entry *entry = &zpci_iomap_start[ZPCI_IDX(dst)];
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u64 req = ZPCI_CREATE_REQ(entry->fh, entry->bar, len);
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u64 offset = ZPCI_OFFSET(dst);
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return __zpci_store_block(src, req, offset);
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}
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static inline int __pcistb_mio(const u64 *data, u64 ioaddr, u64 len, u8 *status)
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{
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int cc = -ENXIO;
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asm volatile (
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" .insn rsy,0xeb00000000d4,%[len],%[ioaddr],%[data]\n"
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"0: ipm %[cc]\n"
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" srl %[cc],28\n"
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"1:\n"
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EX_TABLE(0b, 1b)
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: [cc] "+d" (cc), [len] "+d" (len)
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: [ioaddr] "d" (ioaddr), [data] "Q" (*data)
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: "cc");
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*status = len >> 24 & 0xff;
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return cc;
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}
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int zpci_write_block(volatile void __iomem *dst,
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const void *src, unsigned long len)
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{
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u8 status;
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int cc;
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if (!static_branch_unlikely(&have_mio))
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return zpci_write_block_fh(dst, src, len);
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cc = __pcistb_mio(src, (__force u64) dst, len, &status);
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if (cc)
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zpci_err_insn_addr(0, 'B', cc, status, (__force u64) dst, len);
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return (cc > 0) ? -EIO : cc;
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}
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EXPORT_SYMBOL_GPL(zpci_write_block);
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static inline void __pciwb_mio(void)
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{
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asm volatile (".insn rre,0xb9d50000,0,0\n");
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}
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void zpci_barrier(void)
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{
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if (static_branch_likely(&have_mio))
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__pciwb_mio();
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}
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EXPORT_SYMBOL_GPL(zpci_barrier);
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