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https://gitee.com/bianbu-linux/linux-6.6
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a780e485b5
ALT_UP_B macro sets symbol up_b_offset via .equ to an expression involving another symbol. The macro gets expanded twice when arch/arm/kernel/sleep.S is assembled, creating a scenario where up_b_offset is set to another expression involving symbols while its current value is based on symbols. LLVM integrated assembler does not allow such cases, and based on the documentation of binutils, "Values that are based on expressions involving other symbols are allowed, but some targets may restrict this to only being done once per assembly", so it may be better to avoid such cases as it is not clearly stated which targets should support or disallow them. The fix in this case is simple, as up_b_offset has only one use, so we can replace the use with the definition and get rid of up_b_offset. Link:https://github.com/ClangBuiltLinux/linux/issues/920 Reviewed-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Jian Cai <caij2003@gmail.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
570 lines
12 KiB
C
570 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* arch/arm/include/asm/assembler.h
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*
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* Copyright (C) 1996-2000 Russell King
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*
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* This file contains arm architecture specific defines
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* for the different processors.
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*
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* Do not include any C declarations in this file - it is included by
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* assembler source.
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*/
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#ifndef __ASM_ASSEMBLER_H__
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#define __ASM_ASSEMBLER_H__
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#ifndef __ASSEMBLY__
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#error "Only include this from assembly code"
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#endif
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#include <asm/ptrace.h>
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#include <asm/domain.h>
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#include <asm/opcodes-virt.h>
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#include <asm/asm-offsets.h>
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#include <asm/page.h>
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#include <asm/thread_info.h>
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#define IOMEM(x) (x)
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/*
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* Endian independent macros for shifting bytes within registers.
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*/
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#ifndef __ARMEB__
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#define lspull lsr
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#define lspush lsl
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#define get_byte_0 lsl #0
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#define get_byte_1 lsr #8
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#define get_byte_2 lsr #16
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#define get_byte_3 lsr #24
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#define put_byte_0 lsl #0
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#define put_byte_1 lsl #8
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#define put_byte_2 lsl #16
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#define put_byte_3 lsl #24
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#else
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#define lspull lsl
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#define lspush lsr
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#define get_byte_0 lsr #24
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#define get_byte_1 lsr #16
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#define get_byte_2 lsr #8
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#define get_byte_3 lsl #0
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#define put_byte_0 lsl #24
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#define put_byte_1 lsl #16
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#define put_byte_2 lsl #8
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#define put_byte_3 lsl #0
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#endif
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/* Select code for any configuration running in BE8 mode */
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#ifdef CONFIG_CPU_ENDIAN_BE8
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#define ARM_BE8(code...) code
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#else
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#define ARM_BE8(code...)
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#endif
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/*
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* Data preload for architectures that support it
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*/
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#if __LINUX_ARM_ARCH__ >= 5
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#define PLD(code...) code
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#else
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#define PLD(code...)
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#endif
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/*
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* This can be used to enable code to cacheline align the destination
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* pointer when bulk writing to memory. Experiments on StrongARM and
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* XScale didn't show this a worthwhile thing to do when the cache is not
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* set to write-allocate (this would need further testing on XScale when WA
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* is used).
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*
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* On Feroceon there is much to gain however, regardless of cache mode.
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*/
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#ifdef CONFIG_CPU_FEROCEON
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#define CALGN(code...) code
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#else
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#define CALGN(code...)
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#endif
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#define IMM12_MASK 0xfff
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/*
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* Enable and disable interrupts
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*/
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#if __LINUX_ARM_ARCH__ >= 6
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.macro disable_irq_notrace
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cpsid i
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.endm
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.macro enable_irq_notrace
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cpsie i
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.endm
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#else
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.macro disable_irq_notrace
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msr cpsr_c, #PSR_I_BIT | SVC_MODE
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.endm
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.macro enable_irq_notrace
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msr cpsr_c, #SVC_MODE
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.endm
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#endif
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.macro asm_trace_hardirqs_off, save=1
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#if defined(CONFIG_TRACE_IRQFLAGS)
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.if \save
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stmdb sp!, {r0-r3, ip, lr}
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.endif
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bl trace_hardirqs_off
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.if \save
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ldmia sp!, {r0-r3, ip, lr}
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.endif
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#endif
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.endm
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.macro asm_trace_hardirqs_on, cond=al, save=1
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#if defined(CONFIG_TRACE_IRQFLAGS)
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/*
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* actually the registers should be pushed and pop'd conditionally, but
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* after bl the flags are certainly clobbered
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*/
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.if \save
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stmdb sp!, {r0-r3, ip, lr}
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.endif
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bl\cond trace_hardirqs_on
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.if \save
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ldmia sp!, {r0-r3, ip, lr}
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.endif
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#endif
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.endm
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.macro disable_irq, save=1
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disable_irq_notrace
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asm_trace_hardirqs_off \save
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.endm
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.macro enable_irq
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asm_trace_hardirqs_on
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enable_irq_notrace
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.endm
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/*
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* Save the current IRQ state and disable IRQs. Note that this macro
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* assumes FIQs are enabled, and that the processor is in SVC mode.
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*/
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.macro save_and_disable_irqs, oldcpsr
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#ifdef CONFIG_CPU_V7M
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mrs \oldcpsr, primask
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#else
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mrs \oldcpsr, cpsr
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#endif
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disable_irq
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.endm
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.macro save_and_disable_irqs_notrace, oldcpsr
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#ifdef CONFIG_CPU_V7M
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mrs \oldcpsr, primask
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#else
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mrs \oldcpsr, cpsr
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#endif
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disable_irq_notrace
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.endm
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/*
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* Restore interrupt state previously stored in a register. We don't
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* guarantee that this will preserve the flags.
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*/
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.macro restore_irqs_notrace, oldcpsr
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#ifdef CONFIG_CPU_V7M
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msr primask, \oldcpsr
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#else
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msr cpsr_c, \oldcpsr
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#endif
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.endm
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.macro restore_irqs, oldcpsr
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tst \oldcpsr, #PSR_I_BIT
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asm_trace_hardirqs_on cond=eq
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restore_irqs_notrace \oldcpsr
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.endm
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/*
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* Assembly version of "adr rd, BSYM(sym)". This should only be used to
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* reference local symbols in the same assembly file which are to be
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* resolved by the assembler. Other usage is undefined.
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*/
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.irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
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.macro badr\c, rd, sym
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#ifdef CONFIG_THUMB2_KERNEL
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adr\c \rd, \sym + 1
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#else
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adr\c \rd, \sym
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#endif
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.endm
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.endr
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/*
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* Get current thread_info.
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*/
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.macro get_thread_info, rd
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ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT )
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THUMB( mov \rd, sp )
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THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT )
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mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT
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.endm
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/*
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* Increment/decrement the preempt count.
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*/
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#ifdef CONFIG_PREEMPT_COUNT
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.macro inc_preempt_count, ti, tmp
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ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
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add \tmp, \tmp, #1 @ increment it
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str \tmp, [\ti, #TI_PREEMPT]
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.endm
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.macro dec_preempt_count, ti, tmp
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ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
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sub \tmp, \tmp, #1 @ decrement it
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str \tmp, [\ti, #TI_PREEMPT]
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.endm
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.macro dec_preempt_count_ti, ti, tmp
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get_thread_info \ti
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dec_preempt_count \ti, \tmp
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.endm
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#else
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.macro inc_preempt_count, ti, tmp
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.endm
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.macro dec_preempt_count, ti, tmp
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.endm
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.macro dec_preempt_count_ti, ti, tmp
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.endm
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#endif
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#define USERL(l, x...) \
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9999: x; \
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.pushsection __ex_table,"a"; \
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.align 3; \
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.long 9999b,l; \
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.popsection
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#define USER(x...) USERL(9001f, x)
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#ifdef CONFIG_SMP
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#define ALT_SMP(instr...) \
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9998: instr
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/*
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* Note: if you get assembler errors from ALT_UP() when building with
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* CONFIG_THUMB2_KERNEL, you almost certainly need to use
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* ALT_SMP( W(instr) ... )
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*/
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#define ALT_UP(instr...) \
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.pushsection ".alt.smp.init", "a" ;\
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.long 9998b ;\
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9997: instr ;\
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.if . - 9997b == 2 ;\
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nop ;\
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.endif ;\
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.if . - 9997b != 4 ;\
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.error "ALT_UP() content must assemble to exactly 4 bytes";\
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.endif ;\
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.popsection
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#define ALT_UP_B(label) \
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.pushsection ".alt.smp.init", "a" ;\
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.long 9998b ;\
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W(b) . + (label - 9998b) ;\
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.popsection
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#else
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#define ALT_SMP(instr...)
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#define ALT_UP(instr...) instr
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#define ALT_UP_B(label) b label
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#endif
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/*
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* Instruction barrier
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*/
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.macro instr_sync
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#if __LINUX_ARM_ARCH__ >= 7
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isb
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#elif __LINUX_ARM_ARCH__ == 6
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mcr p15, 0, r0, c7, c5, 4
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#endif
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.endm
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/*
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* SMP data memory barrier
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*/
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.macro smp_dmb mode
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#ifdef CONFIG_SMP
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#if __LINUX_ARM_ARCH__ >= 7
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.ifeqs "\mode","arm"
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ALT_SMP(dmb ish)
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.else
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ALT_SMP(W(dmb) ish)
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.endif
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#elif __LINUX_ARM_ARCH__ == 6
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ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
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#else
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#error Incompatible SMP platform
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#endif
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.ifeqs "\mode","arm"
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ALT_UP(nop)
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.else
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ALT_UP(W(nop))
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.endif
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#endif
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.endm
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#if defined(CONFIG_CPU_V7M)
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/*
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* setmode is used to assert to be in svc mode during boot. For v7-M
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* this is done in __v7m_setup, so setmode can be empty here.
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*/
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.macro setmode, mode, reg
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.endm
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#elif defined(CONFIG_THUMB2_KERNEL)
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.macro setmode, mode, reg
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mov \reg, #\mode
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msr cpsr_c, \reg
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.endm
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#else
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.macro setmode, mode, reg
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msr cpsr_c, #\mode
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.endm
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#endif
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/*
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* Helper macro to enter SVC mode cleanly and mask interrupts. reg is
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* a scratch register for the macro to overwrite.
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*
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* This macro is intended for forcing the CPU into SVC mode at boot time.
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* you cannot return to the original mode.
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*/
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.macro safe_svcmode_maskall reg:req
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#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
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mrs \reg , cpsr
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eor \reg, \reg, #HYP_MODE
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tst \reg, #MODE_MASK
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bic \reg , \reg , #MODE_MASK
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orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
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THUMB( orr \reg , \reg , #PSR_T_BIT )
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bne 1f
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orr \reg, \reg, #PSR_A_BIT
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badr lr, 2f
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msr spsr_cxsf, \reg
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__MSR_ELR_HYP(14)
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__ERET
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1: msr cpsr_c, \reg
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2:
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#else
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/*
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* workaround for possibly broken pre-v6 hardware
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* (akita, Sharp Zaurus C-1000, PXA270-based)
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*/
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setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
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#endif
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.endm
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/*
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* STRT/LDRT access macros with ARM and Thumb-2 variants
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*/
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#ifdef CONFIG_THUMB2_KERNEL
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.macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
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9999:
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.if \inc == 1
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\instr\()b\t\cond\().w \reg, [\ptr, #\off]
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.elseif \inc == 4
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\instr\t\cond\().w \reg, [\ptr, #\off]
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.else
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.error "Unsupported inc macro argument"
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.endif
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.pushsection __ex_table,"a"
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.align 3
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.long 9999b, \abort
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.popsection
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.endm
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.macro usracc, instr, reg, ptr, inc, cond, rept, abort
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@ explicit IT instruction needed because of the label
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@ introduced by the USER macro
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.ifnc \cond,al
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.if \rept == 1
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itt \cond
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.elseif \rept == 2
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ittt \cond
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.else
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.error "Unsupported rept macro argument"
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.endif
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.endif
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@ Slightly optimised to avoid incrementing the pointer twice
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usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
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.if \rept == 2
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usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
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.endif
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add\cond \ptr, #\rept * \inc
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.endm
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#else /* !CONFIG_THUMB2_KERNEL */
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.macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
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.rept \rept
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9999:
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.if \inc == 1
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\instr\()b\t\cond \reg, [\ptr], #\inc
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.elseif \inc == 4
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\instr\t\cond \reg, [\ptr], #\inc
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.else
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.error "Unsupported inc macro argument"
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.endif
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.pushsection __ex_table,"a"
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.align 3
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.long 9999b, \abort
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.popsection
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.endr
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.endm
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#endif /* CONFIG_THUMB2_KERNEL */
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.macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
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usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
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.endm
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.macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
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usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
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.endm
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/* Utility macro for declaring string literals */
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.macro string name:req, string
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.type \name , #object
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\name:
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.asciz "\string"
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.size \name , . - \name
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.endm
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.macro csdb
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#ifdef CONFIG_THUMB2_KERNEL
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.inst.w 0xf3af8014
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#else
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.inst 0xe320f014
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#endif
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.endm
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.macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
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#ifndef CONFIG_CPU_USE_DOMAINS
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adds \tmp, \addr, #\size - 1
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sbcscc \tmp, \tmp, \limit
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bcs \bad
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#ifdef CONFIG_CPU_SPECTRE
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movcs \addr, #0
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csdb
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#endif
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#endif
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.endm
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.macro uaccess_mask_range_ptr, addr:req, size:req, limit:req, tmp:req
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#ifdef CONFIG_CPU_SPECTRE
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sub \tmp, \limit, #1
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subs \tmp, \tmp, \addr @ tmp = limit - 1 - addr
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addhs \tmp, \tmp, #1 @ if (tmp >= 0) {
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subshs \tmp, \tmp, \size @ tmp = limit - (addr + size) }
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movlo \addr, #0 @ if (tmp < 0) addr = NULL
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csdb
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#endif
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.endm
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.macro uaccess_disable, tmp, isb=1
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#ifdef CONFIG_CPU_SW_DOMAIN_PAN
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/*
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* Whenever we re-enter userspace, the domains should always be
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* set appropriately.
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*/
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mov \tmp, #DACR_UACCESS_DISABLE
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mcr p15, 0, \tmp, c3, c0, 0 @ Set domain register
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.if \isb
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instr_sync
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.endif
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#endif
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.endm
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.macro uaccess_enable, tmp, isb=1
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#ifdef CONFIG_CPU_SW_DOMAIN_PAN
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/*
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* Whenever we re-enter userspace, the domains should always be
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* set appropriately.
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*/
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mov \tmp, #DACR_UACCESS_ENABLE
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mcr p15, 0, \tmp, c3, c0, 0
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.if \isb
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instr_sync
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.endif
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#endif
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.endm
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.macro uaccess_save, tmp
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#ifdef CONFIG_CPU_SW_DOMAIN_PAN
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mrc p15, 0, \tmp, c3, c0, 0
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str \tmp, [sp, #SVC_DACR]
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#endif
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.endm
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.macro uaccess_restore
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#ifdef CONFIG_CPU_SW_DOMAIN_PAN
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ldr r0, [sp, #SVC_DACR]
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|
mcr p15, 0, r0, c3, c0, 0
|
|
#endif
|
|
.endm
|
|
|
|
.irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
|
|
.macro ret\c, reg
|
|
#if __LINUX_ARM_ARCH__ < 6
|
|
mov\c pc, \reg
|
|
#else
|
|
.ifeqs "\reg", "lr"
|
|
bx\c \reg
|
|
.else
|
|
mov\c pc, \reg
|
|
.endif
|
|
#endif
|
|
.endm
|
|
.endr
|
|
|
|
.macro ret.w, reg
|
|
ret \reg
|
|
#ifdef CONFIG_THUMB2_KERNEL
|
|
nop
|
|
#endif
|
|
.endm
|
|
|
|
.macro bug, msg, line
|
|
#ifdef CONFIG_THUMB2_KERNEL
|
|
1: .inst 0xde02
|
|
#else
|
|
1: .inst 0xe7f001f2
|
|
#endif
|
|
#ifdef CONFIG_DEBUG_BUGVERBOSE
|
|
.pushsection .rodata.str, "aMS", %progbits, 1
|
|
2: .asciz "\msg"
|
|
.popsection
|
|
.pushsection __bug_table, "aw"
|
|
.align 2
|
|
.word 1b, 2b
|
|
.hword \line
|
|
.popsection
|
|
#endif
|
|
.endm
|
|
|
|
#ifdef CONFIG_KPROBES
|
|
#define _ASM_NOKPROBE(entry) \
|
|
.pushsection "_kprobe_blacklist", "aw" ; \
|
|
.balign 4 ; \
|
|
.long entry; \
|
|
.popsection
|
|
#else
|
|
#define _ASM_NOKPROBE(entry)
|
|
#endif
|
|
|
|
#endif /* __ASM_ASSEMBLER_H__ */
|