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Xilinx PG158 page 80 [1] states that master transaction inhibit bit must be set to properly setup the transaction in QSPI mode. Add the force_irq flag to follow this sequence. [1] https://docs.xilinx.com/r/en-US/pg153-axi-quad-spi/Dual/Quad-SPI-Mode-Transactions Signed-off-by: Vadim Fedorenko <vadfed@meta.com> Link: https://lore.kernel.org/r/20230214135928.1253205-1-vadfed@meta.com Signed-off-by: Mark Brown <broonie@kernel.org>
21 lines
644 B
C
21 lines
644 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __LINUX_SPI_XILINX_SPI_H
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#define __LINUX_SPI_XILINX_SPI_H
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/**
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* struct xspi_platform_data - Platform data of the Xilinx SPI driver
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* @num_chipselect: Number of chip select by the IP.
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* @little_endian: If registers should be accessed little endian or not.
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* @bits_per_word: Number of bits per word.
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* @devices: Devices to add when the driver is probed.
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* @num_devices: Number of devices in the devices array.
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*/
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struct xspi_platform_data {
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u16 num_chipselect;
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u8 bits_per_word;
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struct spi_board_info *devices;
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u8 num_devices;
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bool force_irq;
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};
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#endif /* __LINUX_SPI_XILINX_SPI_H */
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