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8ad43336b5
We now support THP with both 64k and 4K page size configuration for radix. (hash only support THP with 64K page size). Hence we will have CONFIG_TRANSPARENT_HUGEPAGE enabled for both PPC_64K and PPC_4K config. Since we only need large pmd page table with hash configuration (to store the slot information in the second half of the table) restrict the large pmd page table to THP and 64K configs. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Reviewed-by: Anshuman Khandual <khandual@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
210 lines
6.3 KiB
C
210 lines
6.3 KiB
C
#ifndef _ASM_POWERPC_BOOK3S_64_HASH_H
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#define _ASM_POWERPC_BOOK3S_64_HASH_H
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#ifdef __KERNEL__
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/*
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* Common bits between 4K and 64K pages in a linux-style PTE.
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* Additional bits may be defined in pgtable-hash64-*.h
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*
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* Note: We only support user read/write permissions. Supervisor always
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* have full read/write to pages above PAGE_OFFSET (pages below that
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* always use the user access permissions).
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*
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* We could create separate kernel read-only if we used the 3 PP bits
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* combinations that newer processors provide but we currently don't.
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*/
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#define H_PAGE_BUSY 0x00800 /* software: PTE & hash are busy */
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#define H_PTE_NONE_MASK _PAGE_HPTEFLAGS
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#define H_PAGE_F_GIX_SHIFT 57
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#define H_PAGE_F_GIX (7ul << 57) /* HPTE index within HPTEG */
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#define H_PAGE_F_SECOND (1ul << 60) /* HPTE is in 2ndary HPTEG */
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#define H_PAGE_HASHPTE (1ul << 61) /* PTE has associated HPTE */
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#ifdef CONFIG_PPC_64K_PAGES
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#include <asm/book3s/64/hash-64k.h>
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#else
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#include <asm/book3s/64/hash-4k.h>
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#endif
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/*
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* Size of EA range mapped by our pagetables.
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*/
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#define H_PGTABLE_EADDR_SIZE (H_PTE_INDEX_SIZE + H_PMD_INDEX_SIZE + \
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H_PUD_INDEX_SIZE + H_PGD_INDEX_SIZE + PAGE_SHIFT)
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#define H_PGTABLE_RANGE (ASM_CONST(1) << H_PGTABLE_EADDR_SIZE)
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#if defined(CONFIG_TRANSPARENT_HUGEPAGE) && defined(CONFIG_PPC_64K_PAGES)
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/*
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* only with hash 64k we need to use the second half of pmd page table
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* to store pointer to deposited pgtable_t
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*/
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#define H_PMD_CACHE_INDEX (H_PMD_INDEX_SIZE + 1)
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#else
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#define H_PMD_CACHE_INDEX H_PMD_INDEX_SIZE
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#endif
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/*
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* Define the address range of the kernel non-linear virtual area
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*/
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#define H_KERN_VIRT_START ASM_CONST(0xD000000000000000)
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#define H_KERN_VIRT_SIZE ASM_CONST(0x0000100000000000)
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/*
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* The vmalloc space starts at the beginning of that region, and
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* occupies half of it on hash CPUs and a quarter of it on Book3E
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* (we keep a quarter for the virtual memmap)
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*/
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#define H_VMALLOC_START H_KERN_VIRT_START
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#define H_VMALLOC_SIZE (H_KERN_VIRT_SIZE >> 1)
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#define H_VMALLOC_END (H_VMALLOC_START + H_VMALLOC_SIZE)
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/*
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* Region IDs
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*/
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#define REGION_SHIFT 60UL
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#define REGION_MASK (0xfUL << REGION_SHIFT)
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#define REGION_ID(ea) (((unsigned long)(ea)) >> REGION_SHIFT)
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#define VMALLOC_REGION_ID (REGION_ID(H_VMALLOC_START))
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#define KERNEL_REGION_ID (REGION_ID(PAGE_OFFSET))
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#define VMEMMAP_REGION_ID (0xfUL) /* Server only */
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#define USER_REGION_ID (0UL)
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/*
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* Defines the address of the vmemap area, in its own region on
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* hash table CPUs.
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*/
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#define H_VMEMMAP_BASE (VMEMMAP_REGION_ID << REGION_SHIFT)
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#ifdef CONFIG_PPC_MM_SLICES
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#define HAVE_ARCH_UNMAPPED_AREA
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#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
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#endif /* CONFIG_PPC_MM_SLICES */
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/* PTEIDX nibble */
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#define _PTEIDX_SECONDARY 0x8
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#define _PTEIDX_GROUP_IX 0x7
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#define H_PMD_BAD_BITS (PTE_TABLE_SIZE-1)
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#define H_PUD_BAD_BITS (PMD_TABLE_SIZE-1)
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#ifndef __ASSEMBLY__
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#define hash__pmd_bad(pmd) (pmd_val(pmd) & H_PMD_BAD_BITS)
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#define hash__pud_bad(pud) (pud_val(pud) & H_PUD_BAD_BITS)
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static inline int hash__pgd_bad(pgd_t pgd)
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{
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return (pgd_val(pgd) == 0);
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}
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extern void hpte_need_flush(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, unsigned long pte, int huge);
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extern unsigned long htab_convert_pte_flags(unsigned long pteflags);
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/* Atomic PTE updates */
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static inline unsigned long hash__pte_update(struct mm_struct *mm,
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unsigned long addr,
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pte_t *ptep, unsigned long clr,
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unsigned long set,
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int huge)
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{
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__be64 old_be, tmp_be;
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unsigned long old;
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__asm__ __volatile__(
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"1: ldarx %0,0,%3 # pte_update\n\
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and. %1,%0,%6\n\
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bne- 1b \n\
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andc %1,%0,%4 \n\
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or %1,%1,%7\n\
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stdcx. %1,0,%3 \n\
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bne- 1b"
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: "=&r" (old_be), "=&r" (tmp_be), "=m" (*ptep)
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: "r" (ptep), "r" (cpu_to_be64(clr)), "m" (*ptep),
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"r" (cpu_to_be64(H_PAGE_BUSY)), "r" (cpu_to_be64(set))
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: "cc" );
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/* huge pages use the old page table lock */
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if (!huge)
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assert_pte_locked(mm, addr);
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old = be64_to_cpu(old_be);
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if (old & H_PAGE_HASHPTE)
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hpte_need_flush(mm, addr, ptep, old, huge);
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return old;
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}
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/* Set the dirty and/or accessed bits atomically in a linux PTE, this
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* function doesn't need to flush the hash entry
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*/
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static inline void hash__ptep_set_access_flags(pte_t *ptep, pte_t entry)
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{
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__be64 old, tmp, val, mask;
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mask = cpu_to_be64(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_READ | _PAGE_WRITE |
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_PAGE_EXEC | _PAGE_SOFT_DIRTY);
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val = pte_raw(entry) & mask;
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__asm__ __volatile__(
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"1: ldarx %0,0,%4\n\
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and. %1,%0,%6\n\
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bne- 1b \n\
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or %0,%3,%0\n\
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stdcx. %0,0,%4\n\
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bne- 1b"
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:"=&r" (old), "=&r" (tmp), "=m" (*ptep)
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:"r" (val), "r" (ptep), "m" (*ptep), "r" (cpu_to_be64(H_PAGE_BUSY))
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:"cc");
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}
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static inline int hash__pte_same(pte_t pte_a, pte_t pte_b)
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{
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return (((pte_raw(pte_a) ^ pte_raw(pte_b)) & ~cpu_to_be64(_PAGE_HPTEFLAGS)) == 0);
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}
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static inline int hash__pte_none(pte_t pte)
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{
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return (pte_val(pte) & ~H_PTE_NONE_MASK) == 0;
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}
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/* This low level function performs the actual PTE insertion
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* Setting the PTE depends on the MMU type and other factors. It's
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* an horrible mess that I'm not going to try to clean up now but
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* I'm keeping it in one place rather than spread around
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*/
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static inline void hash__set_pte_at(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep, pte_t pte, int percpu)
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{
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/*
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* Anything else just stores the PTE normally. That covers all 64-bit
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* cases, and 32-bit non-hash with 32-bit PTEs.
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*/
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*ptep = pte;
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}
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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extern void hpte_do_hugepage_flush(struct mm_struct *mm, unsigned long addr,
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pmd_t *pmdp, unsigned long old_pmd);
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#else
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static inline void hpte_do_hugepage_flush(struct mm_struct *mm,
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unsigned long addr, pmd_t *pmdp,
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unsigned long old_pmd)
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{
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WARN(1, "%s called with THP disabled\n", __func__);
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}
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#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
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extern int hash__map_kernel_page(unsigned long ea, unsigned long pa,
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unsigned long flags);
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extern int __meminit hash__vmemmap_create_mapping(unsigned long start,
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unsigned long page_size,
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unsigned long phys);
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extern void hash__vmemmap_remove_mapping(unsigned long start,
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unsigned long page_size);
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int hash__create_section_mapping(unsigned long start, unsigned long end);
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int hash__remove_section_mapping(unsigned long start, unsigned long end);
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#endif /* !__ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_BOOK3S_64_HASH_H */
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