Update for v1.0.15

debian/opensbi-spacemit.postinst

@@ -31,9 +31,15 @@ configure)
             OPENSBI_SEEK=0
             ;;
         "/dev/nvme0n1"*)
-            OPENSBI=/dev/mtdblock0
-            # 以KB为单位
-            OPENSBI_SEEK=448
+            if [ ! -e "/dev/mtdblock4" ]; then
+                OPENSBI=/dev/mtdblock0
+                # 以KB为单位
+                OPENSBI_SEEK=448
+            else
+                OPENSBI=/dev/mtdblock4
+                # 以KB为单位
+                OPENSBI_SEEK=0
+            fi
             ;;
         *)
             echo "Unsupported root=$ROOT"
@@ -56,8 +62,9 @@ configure)
     done
 
     # 此前已经做了所有检查
+    set -x
     dd if=/usr/lib/riscv64-linux-gnu/opensbi/generic/fw_dynamic.itb of=$OPENSBI seek=$OPENSBI_SEEK bs=1K && sync
-
+    set +x
     ;;
 esac
 

lib/utils/psci/spacemit/plat/k1x/underly_implement.c

@@ -319,6 +319,26 @@ int spacemit_core_enter_c2(u_register_t mpidr)
 	return 0;
 }
 
+int spacemit_cluster_enter_m2(u_register_t mpidr)
+{
+	unsigned int value;
+
+	/* wait the cpu enter M2 */
+	value = readl((unsigned int *)0xd4282890);
+
+	if (mpidr == 0 || mpidr == 1 || mpidr == 2 || mpidr == 3) {
+		if (value & (1 << 3))
+			return 1;
+	} else if (mpidr == 4 || mpidr == 5 || mpidr == 6 || mpidr == 7) {
+		if (value & (1 << 19))
+			return 1;
+	} else {
+		return 0;
+	}
+
+	return 0;
+}
+
 void spacemit_wait_core_enter_c2(u_register_t mpidr)
 {
 	unsigned int value;

lib/utils/psci/spacemit/plat/plat_pm.c

@@ -147,6 +147,9 @@ static void spacemit_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_st
 		spin_lock(&psciipi_lock);
 
 		if (sbi_hartmask_test_hart(hartid, &psciipi_wait_hmask)) {
+
+			sbi_hartmask_clear_hart(hartid, &psciipi_wait_hmask);
+
 			sbi_ipi_raw_clear(hartid);
 			/* Restore MIE CSR */
 			csr_write(CSR_MIE, saved_mie);
@@ -225,7 +228,7 @@ static int spacemit_validate_power_state(unsigned int power_state,
 static void spacemit_pwr_domain_suspend(const psci_power_state_t *target_state)
 {
 	unsigned int hartid = current_hartid();
-	
+
         /*
          * CSS currently supports retention only at cpu level. Just return
          * as nothing is to be done for retention.
@@ -247,22 +250,27 @@ static void spacemit_pwr_domain_suspend(const psci_power_state_t *target_state)
 		/* disable the tcm */
 		csr_write(CSR_TCMCFG, 0);
 #endif
-		wake_idle_harts(NULL, hartid);
+		if (!spacemit_cluster_enter_m2(PLATFORM_MAX_CPUS_PER_CLUSTER)) {
+			wake_idle_harts(NULL, hartid);
 
-		/* D1P & D2 */
-		csi_flush_l2_cache_hart(0, 0);
-		csi_flush_l2_cache_hart(0, PLATFORM_MAX_CPUS_PER_CLUSTER);
+			csi_flush_l2_cache_hart(0, 0);
+			csi_flush_l2_cache_hart(0, PLATFORM_MAX_CPUS_PER_CLUSTER);
 
-		cci_disable_snoop_dvm_reqs(0);
-		cci_disable_snoop_dvm_reqs(1);
+			cci_disable_snoop_dvm_reqs(0);
+			cci_disable_snoop_dvm_reqs(1);
 
-		/* assert othter cpu & wait other cpu enter c2 */
-		for (u32 i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER * PLATFORM_CLUSTER_COUNT; i++) {
-			if (i != hartid) {
-				spacemit_wait_core_enter_c2(i);
+			/* assert othter cpu & wait other cpu enter c2 */
+			for (u32 i = 0; i < PLATFORM_MAX_CPUS_PER_CLUSTER * PLATFORM_CLUSTER_COUNT; i++) {
+				if (i != hartid) {
+					spacemit_wait_core_enter_c2(i);
+				}
 			}
+		} else {
+			csi_flush_l2_cache_hart(0, 0);
+			cci_disable_snoop_dvm_reqs(0);
 		}
 
+
 		spacemit_assert_cpu(hartid);
 
 		spacemit_top_off(hartid);

lib/utils/psci/spacemit/plat/underly_implement.h

@@ -10,6 +10,7 @@ void spacemit_cluster_off(u_register_t mpidr);
 void spacemit_wakeup_cpu(u_register_t mpidr);
 void spacemit_assert_cpu(u_register_t mpidr);
 int spacemit_core_enter_c2(u_register_t mpidr);
+int spacemit_cluster_enter_m2(u_register_t mpidr);
 void spacemit_wait_core_enter_c2(u_register_t mpidr);
 void spacemit_deassert_cpu(void);