Import orangecms DRAM/SPL info
Signed-off-by: Blizzard Finnegan <blizzardfinnegan@gmail.com>
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commit
51e4c73acb
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Blizzard Finnegan
Blizzard Finnegan
GPG key ID:
1513350E4C45A14F
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284
k1-spl-dram.md
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k1-spl-dram.md
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## Vendor docs
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https://docs.banana-pi.org/en/BPI-F3/BananaPi_BPI-F3
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https://docs.banana-pi.org/en/BPI-F3/GettingStarted_BPI-F3
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https://wiki.banana-pi.org/Banana_Pi_BPI-F3
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## Preparation
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Attempts to get something to run via Ubuntu's/Debian's `fastboot` (version `28.0.2-debian`) directly only results in hanging. \
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There is a script in the SpacemiT download archives though that invokes `fastboot` directly:
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https://archive.spacemit.com/image/k1/flash-all.zip
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A newer version of `fastboot` will do; get it here if your distro doesn't have it:
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https://developer.android.com/tools/releases/platform-tools
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People are puzzled. \
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https://forum.banana-pi.org/t/dfu-and-directly-flashing-the-emmc-using-simpler-tools/18049
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I found notes on the usage of `flashserver` here: \
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https://forum.banana-pi.org/t/emmc-image-installation-fail-fastboot-charmap-exception/18276/3
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Download and extract the latest titanflasher: https://archive.spacemit.com/tools/titanflasher/ \
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From the titantools binary, extract the `flashserver` binary; it's essentially fastboot, but modified.
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```sh
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./titantools_for_linux-1.0.35-beta.AppImage --appimage-extract resources/app/flashserver
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```
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The file will then be at `squashfs-root/resources/app/flashserver`. \
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I recommend putting it elsewhere and have it in your `$PATH`.
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NOTE: The path may change with a newer version of the AppImage. \
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You can mount it like this, which yields the mountpoint, so you can search for it:
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```sh
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./titantools_for_linux-1.0.35-beta.AppImage --appimage-mount
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```
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That will print a path like `/tmp/.mount_titantFtuAIM`. When done, press Ctrl+C to unmount.
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TODO: reverse it.
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## Run SPL/FSBL
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Here is my fork with a few extra changes to get the code to compile (mind the branch):
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https://github.com/orangecms/spacemit-u-boot/tree/v2022.10-k1
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SpacemiT U-Boot creates a file named `FSBL.bin` in the root directory. \
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That is what we can run now using `flasherver`; after `-cmd`, provide the fastboot command to run:
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```sh
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flashserver -cmd "stage FSBL.bin"
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flashserver -cmd "continue"
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```
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For each command, it will ask you to select the port. With just one device attached, that is just `1`. \
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You can also do `flasherver --list` and from there take the `portPath`, which is something like `[3, 2]`. \
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Join the two numbers with a `-`, and provide that as the `-port`:
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```sh
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flashserver -port 3-2 -cmd "getvar version-brom"
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```
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Alternatively, with a recent version of `fastboot` (this here is `35.0.1-11580240`):
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```sh
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fastboot stage FSBL.bin
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fastboot continue
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```
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Here is a log from U-Boot SPL with debug logging (loglevel > 0) enabled in `drivers/ddr/spacemit/k1x/lpddr4_silicon_init.c`:
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```
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fastboot_handle_command: 0002b0a0
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Starting download of 176288 bytes
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usb_tx_bytes : len= 65 pBuf= 0xc083fe88
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usb_rx_bytes : len= 176288 pBuf= 0xc0800000
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usb_tx_bytes : len= 65 pBuf= 0xc083fe88
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usb_rx_bytes : len= 4096 pBuf= 0xc0838720
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SETUP: 0x80 0x6 0x300
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SETUP: 0x80 0x6 0x30a
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SETUP: 0x80 0x6 0x300
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SETUP: 0x80 0x6 0x30a
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fastboot_handle_command: continue
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usb_tx_bytes : len= 65 pBuf= 0xc083fe88
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j...
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U-Boot SPL 2022.10spacemit-g0e3d5c910-dirty (Jul 11 2024 - 03:00:49 +0200)
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ADDR[0xc0000304]=0x00800400 !!!!
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PHY INIT done
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wait DRAM INIT
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DRAM INIT done
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DRAM Mode register Init done.....
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DEBUG-ADDR[0xc0000200]:0xf0001
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DEBUG-ADDR[0xc0000204]:0x0
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DEBUG-ADDR[0xc0000208]:0x800f0001
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DEBUG-ADDR[0xc000020c]:0x0
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DEBUG-ADDR[0xc0000220]:0x5030632
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DEBUG-ADDR[0xc0000224]:0x5030632
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ddr density: 4096 MB
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enter self refresh start .....
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enter self refresh start done .....
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c0000000, 0, 2
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Training start....
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Training init....
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dump margin and setting Before Training....
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Write Leveling.....
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Read Gate Training.....
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Read_gate_training PASS!!
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Read_gate_training PASS!!
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read gate code[0xc0040070]=0x00012121
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read gate code[0xc0040170]=0x00012222
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read gate code[0xc0041070]=0x00011f1f
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read gate code[0xc0041170]=0x00012020
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Read Training.....
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each RX Vref corresponding min margin = 22 22 22 23 23 24 24 24 23 23 23 22 21 18 17 17
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optimize Rx Vref adjust=5 ,corresponding best margin=24
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Again!!! training optimize Fine Rx vref step = 5
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Write Training.....
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each TX Vref corresponding min margin = 19 19 19 20 20 20 20 20 20 20 21 21 21 21 21 21
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optimize Tx Vref adjust=31 ,corresponding best margin=21
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Again!!! training optimize Fine Tx vref step = 31
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Training status[0xC0058000]=0x00000000
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change to 1600
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frequency change done!!!!
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enter self refresh start .....
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enter self refresh start done .....
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c0000000, 1, 2
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Training start....
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Training init....
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dump margin and setting Before Training....
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Write Leveling.....
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Read Gate Training.....
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Read_gate_training PASS!!
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Read_gate_training PASS!!
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read gate code[0xc0044070]=0x00012121
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read gate code[0xc0044170]=0x00012222
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read gate code[0xc0045070]=0x00011f1f
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read gate code[0xc0045170]=0x00012020
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Read Training.....
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each RX Vref corresponding min margin = 14 15 15 16 17 17 17 17 16 16 15 15 14 12 10 9
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optimize Rx Vref adjust=4 ,corresponding best margin=17
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Again!!! training optimize Fine Rx vref step = 4
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Write Training.....
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each TX Vref corresponding min margin = 12 12 12 12 12 12 12 12 13 13 13 13 14 14 14 14
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optimize Tx Vref adjust=33 ,corresponding best margin=14
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Again!!! training optimize Fine Tx vref step = 33
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Training status[0xC0058000]=0x00000000
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change to 2400
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frequency change done!!!!
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enter self refresh start .....
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enter self refresh start done .....
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c0000000, 2, 2
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Training start....
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Training init....
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dump margin and setting Before Training....
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Write Leveling.....
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Read Gate Training.....
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Read_gate_training PASS!!
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Read_gate_training PASS!!
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read gate code[0xc0048070]=0x00012323
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read gate code[0xc0048170]=0x00012323
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read gate code[0xc0049070]=0x00012121
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read gate code[0xc0049170]=0x00012121
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Read Training.....
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each RX Vref corresponding min margin = 8 8 9 9 10 11 11 11 10 10 9 8 8 4 0 0
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optimize Rx Vref adjust=5 ,corresponding best margin=11
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Again!!! training optimize Fine Rx vref step = 5
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Write Training.....
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each TX Vref corresponding min margin = 9 9 9 9 10 10 10 10 9 9 9 9 9 9 9 9
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optimize Tx Vref adjust=25 ,corresponding best margin=10
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Again!!! training optimize Fine Tx vref step = 25
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Training status[0xC0058000]=0x00000000
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change to 2400
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frequency change done!!!!
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lpddr4_silicon_init consume 263ms
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```
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## Run U-Boot main
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After SPL, you can load the U-Boot itb image:
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```sh
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fastboot stage u-boot.itb
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fastboot continue
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```
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continued log:
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```
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.........Boot from fit configuration k1-x_deb1
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## Checking hash(es) for config conf_2 ... OK
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## Checking hash(es) for Image uboot ... crc32+ OK
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## Checking hash(es) for Image fdt_2 ... crc32+ OK
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U-Boot 2022.10spacemit-g0e3d5c910-dirty (Jul 15 2024 - 22:42:54 +0200)
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CPU: rv64imafdcvsu_zicsr_zifencei_zicbom_zihintpause_zba_zbb_zbc_zbs_svpbmt_sstc_sscofpmf
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Model: spacemit k1-x deb1 board
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DRAM: DDR size = 4096 MB
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DDR size = 4096 MB
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DDR size = 4096 MB
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4 GiB
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[RESET]probe start
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[RESET]probe finish
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DCDC_REG1@dcdc1: ; enabling
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DCDC_REG2@dcdc2: ; enabling
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DCDC_REG3@dcdc3: ; enabling
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DCDC_REG4@dcdc4: ; enabling
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DCDC_REG5@dcdc5: ; enabling
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DCDC_REG6@dcdc6: ; enabling
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LDO_REG1@ldo1: ; enabling
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LDO_REG2@ldo2: ; enabling
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LDO_REG3@ldo3: ; enabling
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LDO_REG4@ldo4: ; enabling
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LDO_REG5@ldo5: ; enabling
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LDO_REG6@ldo6: ; enabling
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LDO_REG7@ldo7: ; enabling
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LDO_REG8@ldo8: ; enabling
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LDO_REG9@ldo9: ; enabling
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LDO_REG10@ldo10: ; enabling
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LDO_REG11@ldo11: ; enabling
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SWITCH_REG1@switch1: ; enabling
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Core: 395 devices, 22 uclasses, devicetree: board
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MMC: [RESET]spacemit_reset_set assert=0, id=71
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[RESET]spacemit_reset_set assert=0, id=72
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sdh@d4280000: probe done.
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[RESET]spacemit_reset_set assert=0, id=71
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[RESET]spacemit_reset_set assert=0, id=83
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sdh@d4281000: probe done.
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sdh@d4280000: 0, sdh@d4281000: 2
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Loading Environment from nowhere... OK
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pcie_dw_k1x_probe, 662
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[RESET]spacemit_reset_set assert=0, id=90
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Now init Rterm...
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pcie prot id = 1, porta_init_done = 0
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Now waiting portA resister tuning done...
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porta redonly_reg2: 00005d47
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pcie_rcal = 0x00005d47
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pcie port id = 1, lane num = 2
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Now int init_puphy...
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waiting pll lock...
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Now finish init_puphy....
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pcie_dw_k1x pcie@ca400000: Unable to get phy0pcie_dw_k1x pcie@ca400000: Unable to get phy1PCIEn
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In: serial
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Out: serial
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Err: serial
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ddr_freq_change: ddr frequency change from level 0 to 6
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Change DDR data rate to 2400MT/s
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[RESET]spacemit_reset_set assert=0, id=38
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Default to 100kHz
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EEPROM: TlvInfo v1 len=32
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valid ethaddr: fe:fe:fe:e4:09:17
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Serial number is valid.
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Cannot find TLV data: product_name
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Cannot find TLV data: manufacture_date
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Cannot find TLV data: manufacturer
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Cannot find TLV data: device_version
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Cannot find TLV data: sdk_version
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k1xci_udc: phy_init
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k1xci_udc probe
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k1xci_udc: pullup 1
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-- suspend --
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handle setup GET_DESCRIPTOR, 0x80, 0x6 index 0x0 value 0x100 length 0x40
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handle setup SET_ADDRESS, 0x0, 0x5 index 0x0 value 0xe length 0x0
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handle setup GET_DESCRIPTOR, 0x80, 0x6 index 0x0 value 0x100 length 0x12
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handle setup GET_DESCRIPTOR, 0x80, 0x6 index 0x0 value 0x200 length 0x9
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handle setup GET_DESCRIPTOR, 0x80, 0x6 index 0x0 value 0x200 length 0x20
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handle setup GET_DESCRIPTOR, 0x80, 0x6 index 0x0 value 0x300 length 0xff
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handle setup GET_DESCRIPTOR, 0x80, 0x6 index 0x409 value 0x302 length 0xff
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handle setup GET_DESCRIPTOR, 0x80, 0x6 index 0x409 value 0x301 length 0xff
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handle setup GET_DESCRIPTOR, 0x80, 0x6 index 0x409 value 0x303 length 0xff
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handle setup SET_CONFIGURATION, 0x0, 0x9 index 0x0 value 0x1 length 0x0
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handle setup GET_DESCRIPTOR, 0x80, 0x6 index 0x409 value 0x302 length 0xff
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handle setup GET_DESCRIPTOR, 0x80, 0x6 index 0x409 value 0x304 length 0xff
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handle setup GET_DESCRIPTOR, 0x80, 0x6 index 0x0 value 0x300 length 0x4
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handle setup GET_DESCRIPTOR, 0x80, 0x6 index 0x409 value 0x301 length 0xff
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handle setup GET_DESCRIPTOR, 0x80, 0x6 index 0x0 value 0x300 length 0x4
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handle setup GET_DESCRIPTOR, 0x80, 0x6 index 0x409 value 0x302 length 0xff
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handle setup GET_DESCRIPTOR, 0x80, 0x6 index 0x0 value 0x300 length 0x4
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handle setup GET_DESCRIPTOR, 0x80, 0x6 index 0x409 value 0x303 length 0xff
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```
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Now press Ctrl + C to drop into the U-Boot shell. Enjoy! :-)
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