151 lines
5 KiB
VHDL
151 lines
5 KiB
VHDL
--*****************************************************************************
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--*************************** VHDL Source Code ******************************
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--********* Copyright 2017, Rochester Institute of Technology ***************
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--*****************************************************************************
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--
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-- DESIGNER NAME: Jeanne Christman
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--
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-- LAB NAME: System Design
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--
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-- FILE NAME: KeyGenerator_tb.vhd
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--
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-------------------------------------------------------------------------------
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--
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-- DESCRIPTION
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--
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-- This test bench will provide input to test the KeyGenerator transmitter
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--
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-------------------------------------------------------------------------------
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--
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-- REVISION HISTORY
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--
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-- _______________________________________________________________________
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-- | DATE | USER | Ver | Description |
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-- |==========+======+=====+================================================
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-- | | | |
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-- | 11/27/17 | JWC | 1.0 | original
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-- | | | |
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--
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--*****************************************************************************
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--*****************************************************************************
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_arith.ALL; -- need for conv_std_logic_vector
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USE ieee.std_logic_unsigned.ALL; -- need for "+"
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ENTITY KeyGenerator_tb IS
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END KeyGenerator_tb;
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ARCHITECTURE test OF KeyGenerator_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- if you use a package with the component defined then you do not need this
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COMPONENT KeyGenerator is
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PORT ( clk, reset_n : IN std_logic;
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Seed : IN std_logic_vector(7 downto 0);
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PB, test_mode : IN std_logic;
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GPIO : OUT std_logic);
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END COMPONENT;
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-- define signals for component ports
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SIGNAL clk_tb : std_logic := '0';
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SIGNAL reset_n_tb : std_logic := '0';
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SIGNAL pb_tb : std_logic := '1';
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SIGNAL test_mode_tb : std_logic := '1';
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SIGNAL seed_tb : std_logic_vector(7 DOWNTO 0) := x"00";
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-- Outputs
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SIGNAL gpio_tb : std_logic;
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-- signals for test bench control
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SIGNAL sim_done : boolean := false;
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SIGNAL PERIOD_c : time := 20 ns; -- 50MHz
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BEGIN -- test
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-- component instantiation
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UUT : KeyGenerator
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PORT MAP (
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clk => clk_tb,
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reset_n => reset_n_tb,
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PB => pb_tb,
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test_mode => test_mode_tb,
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Seed => seed_tb,
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--
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GPIO => gpio_tb
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);
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-- This creates an clock_50 that will shut off at the end of the Simulation
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-- this makes a clock_50 that you can shut off when you are done.
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clk_tb <= NOT clk_tb AFTER PERIOD_C/2 WHEN (NOT sim_done) ELSE '0';
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---------------------------------------------------------------------------
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-- NAME: Stimulus
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--
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-- DESCRIPTION:
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-- This process will apply stimulus to the UUT.
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---------------------------------------------------------------------------
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stimulus : PROCESS
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BEGIN
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-- de-assert all input except the reset which is asserted
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reset_n_tb <= '0';
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pb_tb <= '1';
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seed_tb <= x"95";
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-- now lets sync the stimulus to the clk
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-- move stimulus 1ns after clock edge
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WAIT UNTIL clk_tb = '1';
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WAIT FOR 1 ns;
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WAIT FOR PERIOD_c*2;
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-- de-assert reset
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reset_n_tb <= '1';
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WAIT FOR PERIOD_c*2;
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--switches now are at "10010101"
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WAIT FOR PERIOD_c*100;
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pb_tb <= '0';
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WAIT FOR PERIOD_c*10;
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pb_tb <= '1';
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--lock in the seed which is "10010101".
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--The resultant transmit data will drop low for 1us for the start bit and then
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--go "11101001" at a 100ns rate.
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--a 100ns rate means a new bit transmitted every 5 clock cycles
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WAIT FOR PERIOD_c*100;
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seed_tb <= x"12";
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--switches now are at "00010010"
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WAIT FOR PERIOD_c*10;
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pb_tb <= '0';
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WAIT FOR PERIOD_c*10;
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pb_tb <= '1';
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--lock in the seed which is "00010010".
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--The resultant transmit data will drop low for 1us for the start bit and then
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--go "11100100" at a 100ns rate.
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--a 100ns rate means a new bit transmitted every 5 clock cycles
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WAIT FOR PERIOD_c*100;
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sim_done <= true;
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report "simulation complete. This is not a self-checking testbench. You must verify your results manually. The first transmission should be 11101001 and the second should be 11100100.";
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-----------------------------------------------------------------------
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-- This Last WAIT statement needs to be here to prevent the PROCESS
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-- sequence from re starting.
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-----------------------------------------------------------------------
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WAIT;
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END PROCESS stimulus;
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END test;
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