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week4/decode3to8.vhd

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+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+--*************************************************************************************************
+--Please note that VHDL does not allow for multiple architectures in the same file.
+--This file will not compile.
+--It is meant to provide students with the multiple solutions to the same problem
+--************************************************************************************************
+
+--The following is an entity and 8 different architectures for a 3 to 8 decoder
+--A decoder works as follows:
+--one and only one output can be 1
+--the output that is 1 is selected by the binary number formed by the select inputs
+
+--The truth table is below 
+--------------------------------------------------------------------------------------------------
+--  S2 | S1 | S0 || Y7 | Y6 | Y5 | Y4 | Y3 | Y2 | Y1 | Y0 |
+-- ----|----|----||----|----|----|----|----|----|----|----| 
+--   0 |  0 |  0 ||  0 |  0 |  0 |  0 |  0 |  0 |  0 |  1 |
+--   0 |  0 |  0 ||  0 |  0 |  0 |  0 |  0 |  0 |  1 |  0 |  
+--   0 |  0 |  0 ||  0 |  0 |  0 |  0 |  0 |  1 |  0 |  0 |   
+--   0 |  0 |  0 ||  0 |  0 |  0 |  0 |  1 |  0 |  0 |  0 |   
+--   0 |  0 |  0 ||  0 |  0 |  0 |  1 |  0 |  0 |  0 |  0 |   
+--   0 |  0 |  0 ||  0 |  0 |  1 |  0 |  0 |  0 |  0 |  0 |   
+--   0 |  0 |  0 ||  0 |  1 |  0 |  0 |  0 |  0 |  0 |  0 |   
+--   0 |  0 |  0 ||  1 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |   
+---------------------------------------------------------- 
+
+--These models of the 3 to 8 decoder have all of the inputs
+--and outputs as individual std_logic signals
+
+ENTITY decode3to8 IS
+	PORT(s2, s1, s0 : IN STD_LOGIC;
+		  y0, y1, y2, y3, y4, y5, y6, y7  : OUT STD_LOGIC);
+END decode3to8;
+
+--************************************************************************************************
+--this architecture uses a Conditional signal assignment 
+--It also uses an internal std_logic_vector signal to assign all of the outputs at once
+
+ARCHITECTURE cond_signal OF decode3to8 IS
+ 
+   SIGNAL sel_bus   : STD_LOGIC_VECTOR(2 DOWNTO 0);  --this will group the inputs into one signal
+   SIGNAL Y_bus     : STD_LOGIC_VECTOR(7 DOWNTO 0);  --this will create a vector for internal use
+	
+BEGIN
+	
+		sel_bus <= s2 & s1 & s0;    --order is important when concatenating
+		
+		y0 <= Y_bus(0);             --Y_bus is used internally to hold the output
+		y1 <= Y_bus(1);             --values and then assigned to the individual outputs
+		y2 <= Y_bus(2);
+		y3 <= Y_bus(3);
+		y4 <= Y_bus(4);
+		y5 <= Y_bus(5);
+		y6 <= Y_bus(6);
+		y7 <= Y_bus(7);
+
+		Y_bus <= "00000001" WHEN sel_bus = "000" ELSE
+			     "00000010" WHEN sel_bus = "001" ELSE
+				 "00000100" WHEN sel_bus = "010" ELSE
+				 "00001000" WHEN sel_bus = "011" ELSE
+				 "00010000" WHEN sel_bus = "100" ELSE
+			     "00100000" WHEN sel_bus = "101" ELSE
+				 "01000000" WHEN sel_bus = "110" ELSE
+				 "10000000";
+					
+END cond_signal;
+
+--**************************************************************************************************
+--this architecture uses a Conditional signal assignment 
+--It assigns all outputs individually
+
+ ARCHITECTURE cond_signal OF decode3to8 IS
+ 
+   SIGNAL sel_bus   : STD_LOGIC_VECTOR(2 DOWNTO 0);  --this will group the inputs into one signal
+	
+BEGIN
+	
+		sel_bus <= s2 & s1 & s0;    --order is important when concatenating
+
+		Y0 <= '1' WHEN sel_bus = "000" ELSE '0';
+		Y1 <= '1' WHEN sel_bus = "001" ELSE '0';
+		Y2 <= '1' WHEN sel_bus = "010" ELSE '0';
+		Y3 <= '1' WHEN sel_bus = "011" ELSE '0';
+		Y4 <= '1' WHEN sel_bus = "100" ELSE '0';
+		Y5 <= '1' WHEN sel_bus = "101" ELSE '0';
+		Y6 <= '1' WHEN sel_bus = "110" ELSE '0';
+		Y7 <= '1' WHEN sel_bus = "111" ELSE '0';
+				   					
+END cond_signal;
+
+--****************************************************************************************************
+--this architecture uses a selected signal assignment 
+--It also uses an internal std_logic_vector signal to assign all of the outputs at once
+
+ARCHITECTURE sel_signal OF decode3to8 IS
+ 
+   SIGNAL sel_bus   : STD_LOGIC_VECTOR(2 DOWNTO 0);  --this will group the inputs into one signal
+   SIGNAL Y_bus     : STD_LOGIC_VECTOR(7 DOWNTO 0);  --this will create a vector for internal use
+	
+BEGIN
+	
+		sel_bus <= s2 & s1 & s0;    --order is important when concatenating
+		
+		y0 <= Y_bus(0);             --Y_bus is used internally to hold the output
+		y1 <= Y_bus(1);             --values and then assigned to the individual outputs
+		y2 <= Y_bus(2);
+		y3 <= Y_bus(3);
+		y4 <= Y_bus(4);
+		y5 <= Y_bus(5);
+		y6 <= Y_bus(6);
+		y7 <= Y_bus(7);
+
+		WITH sel_bus SELECT
+		Y_bus <= "00000001" WHEN "000",
+			     "00000010" WHEN "001",
+				 "00000100" WHEN "010",
+				 "00001000" WHEN "011",
+				 "00010000" WHEN "100",
+			     "00100000" WHEN "101",
+				 "01000000" WHEN "110",  
+			     "10000000" WHEN OTHERS;
+					
+END sel_signal;
+			
+--****************************************************************************************************
+--this architecture uses a selected signal assignment 
+--It assigns all outputs individually
+
+ARCHITECTURE sel_signal OF decode3to8 IS
+ 
+   SIGNAL sel_bus   : STD_LOGIC_VECTOR(2 DOWNTO 0);  --this will group the inputs into one signal
+	
+BEGIN
+	
+		sel_bus <= s2 & s1 & s0;    --order is important when concatenating
+
+		WITH sel_bus SELECT
+		   Y0 <= '1' WHEN "000",'0' WHEN OTHERS;
+		WITH sel_bus SELECT          --A WITH statement is required for each output
+			Y1 <= '1' WHEN "001",'0' WHEN OTHERS;
+		WITH sel_bus SELECT	 
+			Y2 <= '1' WHEN "010",'0' WHEN OTHERS;
+		WITH sel_bus SELECT
+			Y3 <= '1' WHEN "011",'0' WHEN OTHERS;
+		WITH sel_bus SELECT
+			Y4 <= '1' WHEN "100",'0' WHEN OTHERS;
+		WITH sel_bus SELECT
+			Y5 <= '1' WHEN "101",'0' WHEN OTHERS;
+		WITH sel_bus SELECT
+			Y6 <= '1' WHEN "110",'0' WHEN OTHERS;  
+		WITH sel_bus SELECT
+			Y7 <= '1' WHEN "111",'0' WHEN OTHERS;
+					
+END sel_signal;
+
+--************************************************************************************************
+--this architecture uses a Case Statement
+--It also uses an internal std_logic_vector signal to assign all of the outputs at once
+
+ARCHITECTURE case_arch OF decode3to8 IS
+ 
+   SIGNAL sel_bus   : STD_LOGIC_VECTOR(2 DOWNTO 0);  --this will group the inputs into one signal
+   SIGNAL Y_bus     : STD_LOGIC_VECTOR(7 DOWNTO 0);  --this will create a vector for internal use
+	
+BEGIN
+	
+		sel_bus <= s2 & s1 & s0;    --order is important when concatenating
+		
+		y0 <= Y_bus(0);             --Y_bus is used internally to hold the output
+		y1 <= Y_bus(1);             --values and then assigned to the individual outputs
+		y2 <= Y_bus(2);
+		y3 <= Y_bus(3);
+		y4 <= Y_bus(4);
+		y5 <= Y_bus(5);
+		y6 <= Y_bus(6);
+		y7 <= Y_bus(7);
+		
+   case1:PROCESS(sel_bus)    --sel_bus is read in the process so needs to be in sensitivity list
+	   BEGIN
+		    CASE sel_bus IS
+              WHEN "000" => y_bus <= "00000001";
+			  WHEN "001" => y_bus <= "00000010";
+			  WHEN "010" => y_bus <= "00000100";
+			  WHEN "011" => y_bus <= "00001000";
+			  WHEN "100" => y_bus <= "00010000";
+			  WHEN "101" => y_bus <= "00100000";
+			  WHEN "110" => y_bus <= "01000000";
+			  WHEN OTHERS => y_bus <="10000000";
+			END CASE;
+	  END PROCESS;					
+END case_arch;		
+
+--************************************************************************************************
+--this architecture uses a Case Statement
+--It aassigns each output individually
+
+ARCHITECTURE case_arch OF decode3to8 IS
+ 
+   SIGNAL sel_bus   : STD_LOGIC_VECTOR(2 DOWNTO 0);  --this will group the inputs into one signal
+  
+BEGIN
+	
+		sel_bus <= s2 & s1 & s0;    --order is important when concatenating
+			
+   case2:PROCESS(sel_bus)
+	   BEGIN
+		    y0 <= '0';  --make all inputs '0' to avoid creating a latch           
+		    y1 <= '0';             
+		    y2 <= '0';
+		    y3 <= '0';
+		    y4 <= '0';
+		    y5 <= '0';
+		    y6 <= '0';
+		    y7 <= '0';
+		    CASE sel_bus IS
+              WHEN "000" => y0 <= '1';  --only the selected output is set to 1
+			  WHEN "001" => y1 <= '1';  --all others remain 0 from initial assignment
+			  WHEN "010" => y2 <= '1';
+			  WHEN "011" => y3 <= '1';
+			  WHEN "100" => y4 <= '1';
+			  WHEN "101" => y5 <= '1';
+			  WHEN "110" => y6 <= '1';
+			  WHEN OTHERS => y7 <='1';
+			END CASE;
+	  END PROCESS;					
+END case_arch;				
+
+--************************************************************************************************
+--this architecture uses an if/then/else Statement
+--It also uses an internal std_logic_vector signal to assign all of the outputs at once
+
+ARCHITECTURE case_if OF decode3to8 IS
+ 
+   SIGNAL sel_bus   : STD_LOGIC_VECTOR(2 DOWNTO 0);  --this will group the inputs into one signal
+   SIGNAL Y_bus     : STD_LOGIC_VECTOR(7 DOWNTO 0);  --this will create a vector for internal use
+	
+BEGIN
+	
+		sel_bus <= s2 & s1 & s0;    --order is important when concatenating
+		
+		y0 <= Y_bus(0);             --Y_bus is used internally to hold the output
+		y1 <= Y_bus(1);             --values and then assigned to the individual outputs
+		y2 <= Y_bus(2);
+		y3 <= Y_bus(3);
+		y4 <= Y_bus(4);
+		y5 <= Y_bus(5);
+		y6 <= Y_bus(6);
+		y7 <= Y_bus(7);
+		
+   if1:PROCESS(sel_bus)    --sel_bus is read in the process so needs to be in sensitivity list
+	   BEGIN
+		    IF sel_bus = "000" THEN      --assign all outputs at once
+			     y_bus <= "00000001";
+			 ELSIF sel_bus = "001" THEN
+			     y_bus <= "00000010";
+			 ELSIF sel_bus = "010" THEN 
+			     y_bus <= "00000100";
+			 ELSIF sel_bus = "011" THEN 
+				  y_bus <= "00001000";
+			 ELSIF sel_bus = "100" THEN 
+				  y_bus <= "00010000";
+			 ELSIF sel_bus ="101" THEN 
+				  y_bus <= "00100000";
+			 ELSIF sel_bus = "110" THEN 
+				  y_bus <= "01000000";
+			 ELSE  
+				  y_bus <="10000000";
+			 END IF;
+	  END PROCESS;					
+END case_if;		
+
+--************************************************************************************************
+--this architecture uses a if/then/else Statement
+--It aassigns each output individually
+
+ARCHITECTURE if_arch OF decode3to8 IS
+ 
+   SIGNAL sel_bus   : STD_LOGIC_VECTOR(2 DOWNTO 0);  --this will group the inputs into one signal
+  
+BEGIN
+	
+		sel_bus <= s2 & s1 & s0;    --order is important when concatenating
+			
+   if2:PROCESS(sel_bus)
+	   BEGIN
+		    y0 <= '0';  --make all inputs '0' to avoid creating a latch           
+		    y1 <= '0';             
+		    y2 <= '0';
+		    y3 <= '0';
+		    y4 <= '0';
+		    y5 <= '0';
+		    y6 <= '0';
+		    y7 <= '0';
+		    IF sel_bus = "000" THEN    --assign only the selected output to 1
+			     y0 <= '1';             --all others remain 0
+			 ELSIF sel_bus = "001" THEN
+			     y1 <= '1';
+			 ELSIF sel_bus = "010" THEN 
+			     y2 <= '1';
+			 ELSIF sel_bus = "011" THEN 
+				  y3 <= '1';
+			 ELSIF sel_bus = "100" THEN 
+				  y4 <= '1';
+			 ELSIF sel_bus ="101" THEN 
+				  y5 <= '1';
+			 ELSIF sel_bus = "110" THEN 
+				  y6 <= '1';
+			 ELSE  
+				  y7 <= '1';
+			 END IF;
+	  END PROCESS;					
+END if_arch;				

week4/truthtable.vhd

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+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+--*************************************************************************************************
+--Please note that VHDL does not allow for multiple architectures in the same file.
+--This file will not compile.
+--It is meant to provide students with the multiple solutions to the same problem
+--************************************************************************************************
+
+-- "/" represents an inversion 
+-- The unsimplified SOP equation is : /A/B/C + A/B/C + A/BC
+-- The simplified equation is:  /B/C OR A/B
+
+--        /C  |  C
+--   _________|_____
+--      |     |                                    |&
+--/A/B  |  1  |  0               A ----------------|&
+--   ___|_____|_____                           ____|&____
+--      |     |                                |   |&    |
+--/AB   |  0  |  0                       |\    |         |___|OR
+--   ___|_____|_____             B ------| o---|             |OR____f4
+--      |     |                          |/    |          ___|OR
+-- AB   |  0  |  0                             |___|&    |   |OR
+--   ___|_____|_____                     |\        |&____|
+--      |     |                  C ------| o-------|&
+--A/B   |  1  |  1                       |/        |&
+--      |     |
+--
+ENTITY truthtable IS
+	PORT(a, b, c : IN STD_LOGIC;
+		  f4      : OUT STD_LOGIC);
+END truthtable;
+
+--************************************************************************************************
+--This architecture uses AOI gate statements
+
+ARCHITECTURE AOI OF truthtable IS
+BEGIN
+	
+f4 <= ((NOT b) AND (NOT c)) OR (a AND (NOT b));
+					
+END AOI;
+
+--**************************************************************************************************
+--This architecture uses a Conditional signal assignment 
+
+ARCHITECTURE cond_signal OF truthtable IS
+
+   SIGNAL inputs :STD_LOGIC_VECTOR(2 DOWNTO 0);  --this will group the inputs into one vector
+
+BEGIN
+
+   inputs <= a & b & c;                          --order is important when concatenating
+   f4 <= '1' WHEN inputs = "000" OR inputs = "100" OR inputs = "101" ELSE '0';
+
+				   					
+END cond_signal;
+
+--****************************************************************************************************
+--This architecture uses a selected signal assignment 
+
+ARCHITECTURE sel_signal OF truthtable IS
+ 
+   SIGNAL inputs :STD_LOGIC_VECTOR(2 DOWNTO 0);  --this will group the inputs into one vector
+	
+BEGIN
+	
+   inputs <= a & b & c;                          --order is important when concatenating
+		
+   WITH inputs SELECT
+		f4 <= '1' WHEN "000" | "100" | "101",
+			   '0' WHEN OTHERS;
+					
+END sel_signal;
+--			
+--****************************************************************************************************
+--This architecture uses a case statement 
+--
+ARCHITECTURE case_statement OF truthtable IS
+ 
+   SIGNAL inputs :STD_LOGIC_VECTOR(2 DOWNTO 0);  --this will group the inputs into one vector
+	
+BEGIN
+	
+   inputs <= a & b & c;                          --order is important when concatenating
+		
+case_proc: PROCESS(inputs) IS 
+BEGIN
+   CASE inputs IS 
+	   WHEN "000" | "100" | "101" => f4 <= '1'; 
+		WHEN OTHERS                => f4 <= '0'; 
+	END CASE; 
+END PROCESS; 
+					
+END case_statement;
+
+--****************************************************************************************************
+--This architecture uses a if statement 
+
+ARCHITECTURE if_statement OF truthtable IS
+ 
+   SIGNAL inputs :STD_LOGIC_VECTOR(2 DOWNTO 0);  --this will group the inputs into one vector
+	
+BEGIN
+	
+   inputs <= a & b & c;                          --order is important when concatenating
+		
+if_proc: PROCESS(inputs) IS 
+BEGIN
+   IF (inputs = "000") OR (inputs ="100") THEN   -- You can have multiple conditions on the same line
+	   f4 <= '1'; 
+   ELSIF (inputs = "101") THEN                   -- Or use ELSIF to split them up
+	   f4 <= '1'; 
+	ELSE
+	   f4 <= '0';
+	END IF; 
+END PROCESS; 
+					
+END if_statement;
+					

week7/hexdisplay_tb.vhd

@@ -0,0 +1,89 @@
+--*****************************************************************************
+--***************************  VHDL Source Code  ******************************
+--*********  Copyright 2017, Rochester Institute of Technology  ***************
+--*****************************************************************************
+--
+--  DESIGNER NAME:  Jeanne Christman
+--
+--      FILE NAME:  hexdisplay_tb.vhd
+--
+-------------------------------------------------------------------------------
+--
+--  DESCRIPTION
+--
+--    This test bench will provide input to test an eight bit binary to 
+--    seven-segment display driver.  The input is an 8-bit binary number.
+--    There are two outputs which go to the 7-segment displays to display the 
+--    hexadecimal equivalence of the 8-bit binary number.
+--
+-------------------------------------------------------------------------------
+--
+--  REVISION HISTORY
+--
+--  _______________________________________________________________________
+-- |  DATE    | USER | Ver |  Description                                  |
+-- |==========+======+=====+================================================
+-- |          |      |     |
+-- | 10/10/17 | JWC  | 1.0 | Created
+-- |          |      |     |
+--
+--*****************************************************************************
+--*****************************************************************************
+
+LIBRARY IEEE;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;            
+
+ENTITY hexdisplay_tb IS
+END ENTITY hexdisplay_tb;
+
+ARCHITECTURE test OF hexdisplay_tb IS
+
+--the component name MUST match the entity name of the VHDL module being tested   
+    COMPONENT hexdisplay  
+        PORT ( In_num    : 	in   STD_LOGIC_VECTOR(7 downto 0);      --8-bit input
+               HEX0,HEX1 : 	out  STD_LOGIC_VECTOR(6 downto 0));     --ssd outputs
+    END COMPONENT;
+ 
+    -- testbench signals.  These do not need to be modified
+    SIGNAL In_num_tb          : std_logic_vector(7 DOWNTO 0);
+    --
+    SIGNAL HEX0_tb          : std_logic_vector(6 DOWNTO 0);
+    SIGNAL HEX1_tb          : std_logic_vector(6 DOWNTO 0); 
+    
+BEGIN
+--this must match component above
+    UUT : hexdisplay PORT MAP (  
+        In_num         => In_num_tb,
+        
+        HEX0           => HEX0_tb,
+        HEX1           => HEX1_tb
+        );
+
+    ---------------------------------------------------------------------------
+    -- NAME: Stimulus
+    --
+    -- DESCRIPTION:
+    --    This process will apply the stimulus to the UUT
+    ---------------------------------------------------------------------------
+  Stimulus: Process
+    BEGIN
+            -- create a loop to run through all the combinations of R
+          FOR j IN 0 TO 255 LOOP
+                    -- Assign the R input value
+                    In_num_tb <= STD_LOGIC_VECTOR(to_unsigned(j,8));
+                    wait for 10 ns;
+           End loop;
+                    
+        Report LF& "**************************" &LF&
+        					 "Simulation Complete" &LF&
+        					 "**************************" SEVERITY NOTE;    
+        -----------------------------------------------------------------------
+        -- This last WAIT statement needs to be here to prevent the PROCESS
+        -- sequence from restarting.
+        -----------------------------------------------------------------------
+        WAIT;
+    END PROCESS stimulus;
+
+
+END ARCHITECTURE test;

week7/wave.do

@@ -0,0 +1,21 @@
+radix define radix_ssd {
+"7'b1000000" "0" -color "yellow",
+"7'b1111001" "1" -color "yellow",
+"7'b0100100" "2" -color "yellow",
+"7'b0110000" "3" -color "yellow",
+"7'b0011001" "4" -color "yellow",
+"7'b0010010" "5" -color "yellow",
+"7'b0000010" "6" -color "yellow",
+"7'b1111000" "7" -color "yellow",
+"7'b0000000" "8" -color "yellow",
+"7'b0010000" "9" -color "yellow",
+"7'b0001000" "A" -color "yellow",
+"7'b0000011" "B" -color "yellow",
+"7'b1000110" "C" -color "yellow",
+"7'b0100001" "D" -color "yellow",
+"7'b0000110" "E" -color "yellow",
+"7'b0001110" "F" -color "yellow",
+"7'b0111111" "dash" -color "yellow",
+"7'b1111111" "blank" -color "yellow",
+-default hexadecimal
+}