Add init info
Signed-off-by: Blizzard Finnegan <blizzardfinnegan@gmail.com>
This commit is contained in:
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Signed by:
Blizzard Finnegan
Blizzard Finnegan
GPG key ID:
1513350E4C45A14F
1 changed files with 316 additions and 1 deletions
317
k1-spl-dram.md
317
k1-spl-dram.md
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@ -284,4 +284,319 @@ handle setup GET_DESCRIPTOR, 0x80, 0x6 index 0x409 value 0x303 length 0xff
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Now press Ctrl + C to drop into the U-Boot shell. Enjoy! :-)
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Now press Ctrl + C to drop into the U-Boot shell. Enjoy! :-)
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---
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---
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[source link](https://gist.github.com/orangecms/8624aa82bab4931f787b5eee572f7668)
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[source link](https://gist.github.com/orangecms/8624aa82bab4931f787b5eee572f7668)
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---
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oreboot DRAM init
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NOTE: I reverse engineered the DRAM training blob and translated the other DRAM init code from U-Boot, staged at https://github.com/orangecms/oreboot/tree/all-the-things-wip/src/mainboard/spacemit/k1x/bt0
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NOTE: In order to get the binary with the necessary header, I hacked a bit into the vendor tool, created a custom JSON config for it (see below), and fixed some bits in U-Boot. See https://github.com/orangecms/spacemit-u-boot/tree/v2022.10-k1 - it's a bit messy. I could flash the eMMC with that U-Boot, but then got authentication (header verfiication) errors when booting. No clue why. So just use the tool to create the binary; ./tools/build_binary_file.py -c oreboot.json -o oreboot.bin.
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Will see if we can port the tool to create the header to make it easier to use.
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```JSON
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{
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"_comment": {
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"info": "bootinfo build configuration script",
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"key word": {
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"image": "image definition",
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"module": "image module definition",
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"data": "image item data config"
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}
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},
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"info": {
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"arch": "RISCV64",
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"description": "spacemit k1x fsbl image"
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},
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"image": [
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{
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"module": "ROTPK",
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"data": [
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{
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"pubkey": {
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"name": "rsakeypair0",
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"algorithm": "RSA2048",
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"source": "board/spacemit/k1-x/configs/key/rsakeypair0_prv.key",
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"align": 256
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}
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}
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]
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},
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{
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"module": "image_header",
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"data": [
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{
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"structure": [
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"name, header0, 0",
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"magic, AIHD, 4",
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"version, 1, 1",
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"secure, 0, 1",
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"reserved, 0, 2",
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"imgsize, 0x0200, 8",
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"load_addr, 0x100, 8",
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"pad, 0xA5, 8"
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]
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}
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]
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},
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{
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"module": "image_config",
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"data": [
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{
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"structure": [
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"name, keydata, 0",
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"key_default, 0, 4",
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"table_num, 2, 4",
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{
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"structure": [
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"name, keytable0, 0",
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"key_name, spl, 16",
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"key_id, 0, 4"
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]
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},
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"pad, 0, 452"
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]
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}
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]
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},
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{
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"module": "oem_pubkey",
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"data": [
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{
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"structure": [
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"name, oem_key, 0",
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{
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"pubkey": {
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"name": "spl_pubkey",
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"algorithm": "RSA2048",
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"source": "board/spacemit/k1-x/configs/key/spl_pubkey_prv.key",
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"align": 256
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}
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},
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"reserved, 0, 1792"
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]
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}
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]
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},
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{
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"module": "cert0",
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"data": [
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{
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"signature": {
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"name": "signature0",
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"algorithm": "SHA256+RSA2048",
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"key": "rsakeypair0",
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"source": "header0 + keydata + oem_key",
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"align": 256
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}
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}
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]
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},
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{
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"module": "padding",
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"data": [
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{
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"structure": [
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"pad, 0, 992"
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]
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}
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]
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},
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{
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"module": "spl",
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"data": [
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{
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"structure": [
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"name, header1, 0",
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"magic, AIHD, 4",
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"version, 1, 1",
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"secure, 0, 1",
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"reserved, 0, 2",
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"imgsize, sizeof(fsbl), 8",
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"load_addr, 0x512, 8",
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"pad, 0xA5, 8"
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]
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},
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{
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"file": {
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"name": "fsbl",
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"source": "spacemit-k1x-bt0.bin",
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"align": 32
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}
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},
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{
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"signature": {
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"name": "signature1",
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"algorithm": "SHA256+RSA2048",
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"key": "spl_pubkey",
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"source": "header1 + fsbl",
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"align": 256
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}
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}
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]
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}
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]
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}
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```
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Here is a log.
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NOTE: The panic is intentional.
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```
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oreboot 🦀 bt0
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RISC-V arch 8000000058000001
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RISC-V core vendor: SpacemiT (0x0710)
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RISC-V implementation: X60 (0x1000000049772200)
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RISC-V hart ID 0
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HeaderInfo {
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magic: 0x6ded1e0,
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crc32: 0xc23e034a,
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chipid: 0x9bb6cc1b8baeb641,
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mac_addr: 0xaeba42965924c6c9,
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version: 0x3691b684,
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cs_num: 0xb56abde1,
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}
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dump 1024 bytes @c0800040
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a4f0e0ba5793715641938afc43a1adc23d3e945629b111c817037cec782476ec
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d4a3be098fb5cb75d4191c2d6b87fe2e10593975ba5739c37345d04d47b98ff2
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14cdbdc2fff228183c0c9a9b2099766740719c70cd018b7b30503e01fdd6dd40
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db66d04e65f9f9a9e1f08edead41df8d84556dc989ec7f4e82b9198cf5eec9ef
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7913086b2bfff2855a6525fac8cfed30a89b6a69c951276fc2c7a412118fac42
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8c7bd55f0dbed9230717a3538a920ee32fa189a6ea79956a702e391916745007
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414948440100000000020000000000000001000000000000a5a5a5a5a5a5a5a5
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000000000200000073706c000000000000000000000000000000000000000000
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0000000000000000000000000000000000000000000000000000000000000000
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0000000000000000000000000000000000000000000000000000000000000000
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0000000000000000000000000000000000000000000000000000000000000000
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0000000000000000000000000000000000000000000000000000000000000000
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0000000000000000000000000000000000000000000000000000000000000000
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0000000000000000000000000000000000000000000000000000000000000000
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0000000000000000000000000000000000000000000000000000000000000000
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0000000000000000000000000000000000000000000000000000000000000000
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0000000000000000000000000000000000000000000000000000000000000000
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0000000000000000000000000000000000000000000000000000000000000000
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0000000000000000000000000000000000000000000000000000000000000000
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0000000000000000000000000000000000000000000000000000000000000000
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0000000000000000000000000000000000000000000000000000000000000000
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0000000000000000000000000000000000000000000000000000000000000000
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d263462f1b7be1bbc2a160f5ece41575781d7120b3c95101927eca04e9d5c47e
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c8639b0d530a14ceada30910d9add7b04739c7d7dcba696ae1efff835e53ec40
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fd50f916c7d2d6c9c004388fb574e38eef23ae58eb591fad0aff47a4c82720b5
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eb0649b58b5a664db8a088ad6a9a3f88951618380e9b2a9368f9449a0c3b9227
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3cb179c42baaa309375797cd2894a341b557b7fcdef90ede70a7b5b7abac917f
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1dec10dfe100426ebc1571062c154934856acc84f38f6dae0d66a436e25be1db
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f819a9193c07a8a594a4d667a16d8397a4203705502929fadd603f9f63f864da
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8d2dedf8fee3cb4c330137fcca99e6cbf8e6eebced7fe3dcf42e5fd99dbaab3d
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0000000000000000000000000000000000000000000000000000000000000000
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0000000000000000000000000000000000000000000000000000000000000000
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ADDR[0xc0000304]=0x00800400
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PHY INIT done
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wait DRAM INIT
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DRAM INIT done
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DRAM Mode register Init done.
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DDR size (density): 4096MB
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MR 8: 18
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DEBUG-ADDR[0xc0000200]:0x000f0001
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DEBUG-ADDR[0xc0000204]:0x00000000
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DEBUG-ADDR[0xc0000208]:0x800f0001
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DEBUG-ADDR[0xc000020c]:0x00000000
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DEBUG-ADDR[0xc0000220]:0x05030632
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DEBUG-ADDR[0xc0000224]:0x05030632
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self refresh start
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self refresh done
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Training start...
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Training init...
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Dump margin and setting before training...
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write leveling
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read gate train
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read gate training pass
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read gate training pass
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0xc0040070 = 0x00012121
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0xc0040170 = 0x00012222
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0xc0041070 = 0x00011f1f
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0xc0041170 = 0x00012020
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read training
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each RX Vref corresponding min margin
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00: 22, 01: 22, 02: 22, 03: 23,
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04: 23, 05: 24, 06: 24, 07: 24,
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08: 24, 09: 23, 10: 23, 11: 22,
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12: 21, 13: 18, 14: 17, 15: 16,
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optimize RX Vref adjust = 5, corresponding best margin = 24
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Optimize fine RX vref step: 5
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write training
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each TX Vref corresponding min margin
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00: 20, 01: 20, 02: 20, 03: 20,
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04: 20, 05: 20, 06: 20, 07: 20,
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08: 20, 09: 20, 10: 20, 11: 20,
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12: 20, 13: 20, 14: 20, 15: 20,
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optimize TX Vref adjust = 21, corresponding best margin = 29
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Optimize fine TX vref step: 21
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Training status [0xc0058000]=0x00000000
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change to 1600
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frequency change done!
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self refresh start
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self refresh done
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Training start...
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Training init...
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Dump margin and setting before training...
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write leveling
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read gate train
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read gate training pass
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read gate training pass
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0xc0044070 = 0x00012222
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0xc0044170 = 0x00012222
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0xc0045070 = 0x00012020
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0xc0045170 = 0x00012020
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read training
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each RX Vref corresponding min margin
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00: 14, 01: 15, 02: 15, 03: 16,
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04: 16, 05: 17, 06: 17, 07: 17,
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08: 17, 09: 16, 10: 16, 11: 15,
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12: 14, 13: 11, 14: 10, 15: 9,
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optimize RX Vref adjust = 5, corresponding best margin = 17
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Optimize fine RX vref step: 5
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write training
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each TX Vref corresponding min margin
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00: 12, 01: 12, 02: 12, 03: 12,
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04: 12, 05: 12, 06: 12, 07: 12,
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08: 12, 09: 12, 10: 12, 11: 12,
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12: 12, 13: 12, 14: 12, 15: 12,
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optimize TX Vref adjust = 21, corresponding best margin = 30
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Optimize fine TX vref step: 21
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Training status [0xc0058000]=0x00000000
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change to 2400
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frequency change done!
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self refresh start
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self refresh done
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Training start...
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Training init...
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Dump margin and setting before training...
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write leveling
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read gate train
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read gate training pass
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read gate training pass
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0xc0048070 = 0x00012323
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0xc0048170 = 0x00012323
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0xc0049070 = 0x00012121
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0xc0049170 = 0x00012121
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read training
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each RX Vref corresponding min margin
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00: 8, 01: 8, 02: 9, 03: 9,
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04: 10, 05: 10, 06: 11, 07: 10,
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08: 10, 09: 10, 10: 9, 11: 8,
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12: 8, 13: 4, 14: 0, 15: 0,
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optimize RX Vref adjust = 6, corresponding best margin = 11
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Optimize fine RX vref step: 6
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write training
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each TX Vref corresponding min margin
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00: 10, 01: 10, 02: 10, 03: 10,
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04: 10, 05: 10, 06: 10, 07: 10,
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08: 10, 09: 10, 10: 10, 11: 10,
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12: 10, 13: 10, 14: 10, 15: 10,
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optimize TX Vref adjust = 21, corresponding best margin = 31
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Optimize fine TX vref step: 21
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Training status [0xc0058000]=0x00000000
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change to 2400
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frequency change done!
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[bt0] panic in 'src/mainboard/spacemit/k1x/bt0/src/dram.rs' line 1589
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[bt0] TODO
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```
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Loading…
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Reference in a new issue