Coursework for HDL Lab
  • Verilog 39.9%
  • VHDL 34.7%
  • Tcl 16.5%
  • Stata 7.7%
  • HTML 0.6%
  • Other 0.6%
Find a file
2023-12-06 16:52:08 -05:00
lab1 Lab 1 complete 2023-09-11 17:40:54 -04:00
lab2 Restore downloaded architecture to correct dir 2023-09-18 17:02:29 -04:00
lab3 Update testbench to run properly 2023-09-27 16:15:29 -04:00
lab4 Update 7seg defs 2023-10-04 18:29:28 +00:00
lab5 Complete lab 5 2023-10-17 11:33:22 -04:00
lab6 Add reset case for memory 2023-10-25 15:56:17 -04:00
lab7 Add reset flag for op counter 2023-11-13 15:58:03 -05:00
lab8 insert forgotten begin 2023-12-06 16:52:08 -05:00
tips/hdl Update downloaded zip, potentially mif file 2023-11-13 15:48:05 -05:00
DE0-CV-pintable.pdf Add documentation for DE0 board 2023-09-25 14:18:39 -04:00
DE0_CV_User_Manual.pdf Add documentation for DE0 board 2023-09-25 14:18:39 -04:00
DE1-SoC_User_manual.pdf Copy previous lab to new lab folder 2023-10-02 13:23:40 -04:00
LICENSE Initial commit 2023-08-21 09:37:59 -04:00
README.md Initial commit 2023-08-21 09:37:59 -04:00

cpet-343-01l2-coursework

Coursework for HDL Lab