Init lab6
lab5top has been copied over for quick-reference
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43
lab6/src/alu.vhd
Executable file
43
lab6/src/alu.vhd
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-------------------------------------------------------------------------------
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-- Dr. Kaputa
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-- arithmatic logic unit
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity alu is
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port (
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clk : in std_logic;
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reset : in std_logic;
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a : in std_logic_vector(7 downto 0);
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b : in std_logic_vector(7 downto 0);
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op : in std_logic_vector(1 downto 0); -- 00: add, 01: sub, 10: mult, 11: div
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result : out std_logic_vector(7 downto 0)
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);
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end alu;
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architecture beh of alu is
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signal result_temp : std_logic_vector(15 downto 0):= (others => '0');
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begin
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process(clk,reset)
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begin
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if (reset = '1') then
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result <= (others => '0');
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elsif (clk'event and clk = '1') then
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if (op = "00") then
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result <= std_logic_vector(unsigned(a) + unsigned(b));
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elsif (op = "01") then
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result <= std_logic_vector(unsigned(a) - unsigned(b));
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elsif (op = "10") then
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result_temp <= std_logic_vector(unsigned(a) * unsigned(b));
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result <= result_temp(7 downto 0);
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elsif (op = "11") then
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result_temp <= std_logic_vector(unsigned("00000000" & a) / unsigned("00000000" & b));
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result <= result_temp(7 downto 0);
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end if;
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end if;
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end process;
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end beh;
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37
lab6/src/double_buffer.vhd
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37
lab6/src/double_buffer.vhd
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-------------------------------------------------------------------------------
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-- Blizzard Finnegan
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-- S/R flip-flop
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity double_buffer is
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generic (
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bits : integer := 4
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);
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port(
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d : in std_logic_vector(bits - 1 downto 0);
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clk : in std_logic;
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reset : in std_logic;
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q : out std_logic_vector(bits - 1 downto 0)
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);
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end entity double_buffer;
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architecture arch of double_buffer is
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signal d_buf : std_logic_vector(bits - 1 downto 0);
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begin
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process(clk, reset)
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begin
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if(reset = '1') then
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q <= (others => '0');
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d_buf <= (others => '0');
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elsif (clk'event and clk = '1') then
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d_buf <= d;
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q <= d_buf;
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end if;
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end process;
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end arch;
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76
lab6/src/double_dabble.vhd
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76
lab6/src/double_dabble.vhd
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-------------------------------------------------------------------------------
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-- Dr. Kaputa
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-- double_dabble demo
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity double_dabble is
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port (
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result_padded : in std_logic_vector(11 downto 0);
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ones : out std_logic_vector(3 downto 0);
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tens : out std_logic_vector(3 downto 0);
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hundreds : out std_logic_vector(3 downto 0)
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);
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end double_dabble;
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architecture beh of double_dabble is
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begin
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bcd1: process(result_padded)
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-- temporary variable
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variable temp : STD_LOGIC_VECTOR (11 downto 0);
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-- variable to store the output BCD number
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-- organized as follows
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-- thousands = bcd(15 downto 12)
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-- hundreds = bcd(11 downto 8)
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-- tens = bcd(7 downto 4)
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-- units = bcd(3 downto 0)
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variable bcd : UNSIGNED (15 downto 0) := (others => '0');
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-- by
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-- https://en.wikipedia.org/wiki/Double_dabble
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begin
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-- zero the bcd variable
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bcd := (others => '0');
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-- read input into temp variable
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temp(11 downto 0) := result_padded;
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-- cycle 12 times as we have 12 input bits
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-- this could be optimized, we dont need to check and add 3 for the
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-- first 3 iterations as the number can never be >4
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for i in 0 to 11 loop
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if bcd(3 downto 0) > 4 then
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bcd(3 downto 0) := bcd(3 downto 0) + 3;
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end if;
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if bcd(7 downto 4) > 4 then
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bcd(7 downto 4) := bcd(7 downto 4) + 3;
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end if;
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if bcd(11 downto 8) > 4 then
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bcd(11 downto 8) := bcd(11 downto 8) + 3;
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end if;
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-- thousands can't be >4 for a 12-bit input number
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-- so don't need to do anything to upper 4 bits of bcd
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-- shift bcd left by 1 bit, copy MSB of temp into LSB of bcd
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bcd := bcd(14 downto 0) & temp(11);
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-- shift temp left by 1 bit
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temp := temp(10 downto 0) & '0';
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end loop;
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-- set outputs
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ones <= STD_LOGIC_VECTOR(bcd(3 downto 0));
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tens <= STD_LOGIC_VECTOR(bcd(7 downto 4));
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hundreds <= STD_LOGIC_VECTOR(bcd(11 downto 8));
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--thousands <= STD_LOGIC_VECTOR(bcd(15 downto 12));
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end process bcd1;
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end beh;
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238
lab6/src/lab5top.vhd
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238
lab6/src/lab5top.vhd
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-------------------------------------------------------------------------------
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-- Blizzard Finnegan
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-- 8-bit 2 function calc w/ double-dabble [top-level design]
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity top is
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port(
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clk : in std_logic;
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reset : in std_logic;
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input_switches : in std_logic_vector(7 downto 0);
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state_cycle : in std_logic;
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state_indicator : out std_logic_vector(3 downto 0);
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hundreds_disp : out std_logic_vector(6 downto 0);
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tens_disp : out std_logic_vector(6 downto 0);
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ones_disp : out std_logic_vector(6 downto 0)
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);
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end top;
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architecture behaviour of top is
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component double_dabble is
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port (
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result_padded : in std_logic_vector(11 downto 0);
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ones : out std_logic_vector(3 downto 0);
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tens : out std_logic_vector(3 downto 0);
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hundreds : out std_logic_vector(3 downto 0)
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);
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end component;
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component generic_adder_beh is
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generic (
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bits : integer := 4
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);
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port (
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a : in std_logic_vector(bits-1 downto 0);
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b : in std_logic_vector(bits-1 downto 0);
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cin : in std_logic;
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sum : out std_logic_vector(bits-1 downto 0);
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cout : out std_logic
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);
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end component;
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component double_buffer is
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generic (
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bits : integer := 3
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);
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port(
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d : in std_logic_vector(bits - 1 downto 0);
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clk : in std_logic;
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reset : in std_logic;
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q : out std_logic_vector(bits - 1 downto 0)
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);
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end component;
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component seven_seg is
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port (
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clk : in std_logic;
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reset : in std_logic;
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bcd : in std_logic_vector(3 downto 0);
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seven_seg_out : out std_logic_vector(6 downto 0)
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);
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end component;
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signal a_store, b_store, show_add, show_sub, add_carry, sub_carry, state_cycle_z, state_cycle_zz, state_cycle_zzz, state_cycle_en : std_logic;
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signal count_out: std_logic_vector(1 downto 0);
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signal ones, tens, hundreds : std_logic_vector(3 downto 0);
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signal input_zz : std_logic_vector(7 downto 0);
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signal a, b, sub_b, add_out, sub_out: std_logic_vector(8 downto 0);
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signal padded_add, padded_sub, padded_input, mux_disp: std_logic_vector(11 downto 0);
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begin
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padded_add <= "000" & add_out;
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padded_sub <= "000" & sub_out;
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padded_input <= "0000" & input_zz;
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sub_b <= not b;
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state_indicator <= ( 0 => a_store,
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1 => b_store,
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2 => show_add,
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3 => show_sub);
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state_cycle_en <= state_cycle_zzz and (not state_cycle_zz);
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a_buffer: process(clk,a_store,reset)
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begin
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if (reset = '1') then
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a <= ( others => '0' );
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elsif (rising_edge(clk)) then
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if ( a_store = '1' ) then
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a <= '0' & input_zz;
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end if;
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end if;
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end process;
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b_buffer: process(clk,b_store,reset)
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begin
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if (reset = '1') then
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b <= ( others => '0' );
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elsif (rising_edge(clk)) then
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if ( b_store = '1' ) then
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b <= '0' & input_zz;
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end if;
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end if;
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end process;
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input_buffer: double_buffer
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generic map (
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bits => 8
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)
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port map(
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d => input_switches,
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q => input_zz,
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clk => clk,
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reset => reset
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);
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adder: generic_adder_beh
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generic map(
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bits => 9
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)
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port map(
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a => a,
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b => b,
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cin => '0',
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sum => add_out,
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cout => add_carry
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);
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subtractor: generic_adder_beh
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generic map(
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bits => 9
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)
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port map(
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a => a,
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b => sub_b,
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cin => '1',
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sum => sub_out,
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cout => sub_carry
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);
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state_cycle_buffer: process(clk,state_cycle)
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begin
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if (reset = '1') then
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state_cycle_z <= '0';
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state_cycle_zz <= '0';
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state_cycle_zzz <= '0';
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elsif rising_edge(clk) then
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state_cycle_z <= state_cycle;
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state_cycle_zz <= state_cycle_z;
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state_cycle_zzz <= state_cycle_zz;
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end if;
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end process;
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counter: process(state_cycle_en)
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begin
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if(reset = '1') then
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count_out <= (others => '0');
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elsif (rising_edge(state_cycle_en)) then
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count_out <= std_logic_vector(unsigned(count_out) + 1);
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end if;
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end process;
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selector: process(count_out)
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begin
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case count_out is
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when "00" =>
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a_store <= '1';
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b_store <= '0';
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show_add <= '0';
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show_sub <= '0';
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when "01" =>
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a_store <= '0';
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b_store <= '1';
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show_add <= '0';
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show_sub <= '0';
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when "10" =>
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a_store <= '0';
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b_store <= '0';
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show_add <= '1';
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show_sub <= '0';
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when "11" =>
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a_store <= '0';
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b_store <= '0';
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show_add <= '0';
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show_sub <= '1';
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when others =>
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a_store <= '1';
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b_store <= '0';
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show_add <= '0';
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show_sub <= '0';
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end case;
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end process;
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mux: process(a_store, b_store, show_add, show_sub)
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begin
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if (a_store = '1' or b_store = '1') then
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mux_disp <= padded_input;
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elsif (show_add = '1') then
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mux_disp <= padded_add;
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elsif (show_sub = '1') then
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mux_disp <= padded_sub;
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end if;
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end process;
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bcd: double_dabble
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port map(
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result_padded => mux_disp,
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ones => ones,
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tens => tens,
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hundreds => hundreds
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);
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show_hundreds: seven_seg
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port map (
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clk => clk,
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reset => reset,
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bcd => hundreds,
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seven_seg_out => hundreds_disp
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);
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show_tens: seven_seg
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port map (
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clk => clk,
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reset => reset,
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bcd => tens,
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seven_seg_out => tens_disp
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);
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show_ones: seven_seg
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port map (
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clk => clk,
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reset => reset,
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bcd => ones,
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seven_seg_out => ones_disp
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);
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end behaviour;
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38
lab6/src/memory.vhd
Executable file
38
lab6/src/memory.vhd
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-------------------------------------------------------------------------------
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-- Dr. Kaputa
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-- memory
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity memory is
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generic (addr_width : integer := 2;
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data_width : integer := 4);
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port (
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clk : in std_logic;
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we : in std_logic;
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addr : in std_logic_vector(addr_width - 1 downto 0);
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din : in std_logic_vector(data_width - 1 downto 0);
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dout : out std_logic_vector(data_width - 1 downto 0)
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);
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end memory;
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architecture beh of memory is
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-- signal declarations
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type ram_type is array ((2 ** addr_width -1) downto 0) of std_logic_vector(data_width -1 downto 0);
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signal RAM : ram_type := (others => (others => '0'));
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begin
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process(clk)
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begin
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if (clk'event and clk = '1') then
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if (we = '1') then
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RAM(to_integer(unsigned(addr))) <= din;
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end if;
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dout <= RAM(to_integer(unsigned(addr)));
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end if;
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end process;
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end beh;
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48
lab6/src/seven_seg.vhd
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48
lab6/src/seven_seg.vhd
Normal file
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-------------------------------------------------------------------------------
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-- Blizzard Finnegan
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-- Binary Coded Decimal to 7-Segment; single digit translation (0-F)
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity seven_seg is
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port (
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clk : in std_logic;
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reset : in std_logic;
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bcd : in std_logic_vector(3 downto 0);
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seven_seg_out : out std_logic_vector(6 downto 0)
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);
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end seven_seg;
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architecture beh of seven_seg is
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begin
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process(clk,reset)
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begin
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if (reset = '1') then
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seven_seg_out <= "1111111";
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elsif (clk'event and clk = '1') then
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case bcd is
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when "0000" => seven_seg_out <= "1000000";
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when "0001" => seven_seg_out <= "1111001";
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when "0010" => seven_seg_out <= "0100100";
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when "0011" => seven_seg_out <= "0110000";
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when "0100" => seven_seg_out <= "0011001";
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when "0101" => seven_seg_out <= "0010010";
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when "0110" => seven_seg_out <= "0000010";
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when "0111" => seven_seg_out <= "1111000";
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when "1000" => seven_seg_out <= "0000000";
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when "1001" => seven_seg_out <= "0011000";
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when "1010" => seven_seg_out <= "0001000";
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when "1011" => seven_seg_out <= "0100001";
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when "1100" => seven_seg_out <= "0110011";
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when "1101" => seven_seg_out <= "0000011";
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when "1110" => seven_seg_out <= "0000110";
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when "1111" => seven_seg_out <= "0001110";
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when others => seven_seg_out <= "1111111";
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end case;
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end if;
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end process;
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end beh;
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Reference in a new issue