Bus structure notes

busStructure.md

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+# Busses
+
+There's a research project on an assigned bus.
+
+A bus is a multi-wire path that transfers information.
+A basic bus contains a group of address lines, a group of data lines, and a group of control lines.
+
+The common bus we've been using this semester is the Avalon interface.
+
+The bus is the wires connecting devices.
+The protocol is how we stack up data.
+
+Address lines distribute addresses.
+Data lines distribute data.
+Control lines are everything else, including but not limited to:
+- Clock
+- Reset
+- Read
+- Write
+- Acknowledge
+
+Bus examples:
+- ISA
+- EISA
+- PCI
+- PCIE
+- SPI
+- I2C
+- USB
+- SDIO
+- JTAG
+- RS232
+- Ethernet
+- CAN
+
+Talk about both the physical bus and the comms protocol.
+
+Asynchronous busses exist, and are nice because we can communicate over longer wires, but they're slower because we need to handshake.
+Common in cleanroom applications, or physically large designs (i.e. running from front to back of a vehicle).
+
+Synchronous busses also exist, and are nice because they're fast, but communcation over longer wires sucks.
+Also, all the devices need the same clock (or a faster clock that can slow down using a FIFO).
+
+Useful terminology:
+- Bandwidth: bits/sec or bytes/sec; max theoretical
+- Effective bandwidth: bits/sec or bytes/sec; realistic estimation of bandwidth rather than raw bandwidth
+- control devices: Number of devices that can initiate info transfers/requests on the bus
+- peripheral devices: number of devices that can only respond to control devices
+- hybrid devices: number of devices that can act as either a control or peripheral
+
+## Tri-State Buffer
+
+Recieves 2 logic states but can produce 3 different output states; high, low, and high-impedance.
+Allows devices to control when it drives info to the bus.
+Often used to release a bus.
+
+## Bus Arbiter
+
+Determines which control gets access to a bus; only required in a multi-control system.
+May be centralised or decentralised.
+
+Arbitration will either happen before the control finishes a transfer (non-hidden) or after the control finishes a transfer (hidden).
+
+## Bus Parking
+
+Arbiter defaults to a controller when nobody wants it.
+Can be used to provide high priority controllers with lower latency.
+
+Controller asserts a request to the arbiter *during the transfer*, and the arbiter asserts a grant when relevant.
+Controller can only transfer over a bus when given a grant.
+If a grant is removed, transfer still allowed to finish.
+
+Burst transactions are extant, and transfer large amounts of data.
+
+Split transaction bus allows multiple controllers to communicate during each others downtime.
+
+Bus Bridges separate high performance devices from low performance devices. 
+Essentially frees up the high performance devices to do other stuff instead.
+
+# Presentation notes
+
+- 5-10 minutes
+- application area
+- bandwidth (ideal and actual)
+- clocking rates
+- signalling tech
+- signalling voltage
+- max device support
+- signals required
+- topology (if applicable)

presentationNotes.md

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+# I2C
+
+- Application area: "dumb" devices
+- Bandwidth:
+- Clock rate:
+- Signalling tech:
+- Signalling voltage:
+- Max device support:
+- Signals required:
+- Topology: spider(?)