generated from rit-ecet-notes/new-course
Embedded Systems Design 1 Coursework
- Verilog 32.2%
- C 28.9%
- SystemVerilog 11.4%
- HTML 10.4%
- VHDL 6.6%
- Other 10.2%
| cpet-561-01@9178d207a4 | ||
| cpet-561-01l1@1e81b63298 | ||
| demos | ||
| labDocs | ||
| .gitmodules | ||
| busStructure.md | ||
| finalReview.md | ||
| LICENSE | ||
| notes.md | ||
| presentationNotes.md | ||
| README.md | ||
| timingAnalysis.md | ||
[COURSE NUMBER] - Course Name
- Time-block
- Professor