Init with first project
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16
README.md
16
README.md
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# icefunVHDL
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Tinkering with the iceFUN FPGA board, based on the iCE40-HX8K FPGA
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Tinkering with the iceFUN FPGA board, based on the iCE40-HX8K FPGA.
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This work is loosely based on the provided code distributed at [the DevanTech github repository](https://github.com/devantech/iceFUN). Since I'm not familiar with VHDL, this repository will be used to both write VHDL for the board, and slowly work my way up to learning Verliog.
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Tools used:
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- [yosys](https://github.com/YosysHQ/yosys)
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- [GHDL](https://github.com/ghdl/ghdl)
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- [GHDL plugin for yosys](https://github.com/ghdl/ghdl-yosys-plugin)
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- [nextpnr-ice40](https://github.com/YosysHQ/nextpnr)
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- [iceFUNprog](https://github.com/devantech/iceFUNprog)
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At time of writing, `iceFUNprog` is necessary on my specific setup, as `openFPGAloader` erroneously claims `unable to open ftdi device: -3 (device not found)`.
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Currently working projects:
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- SimpleCounter: Counter using clock divider for input, and 8x4 LED matrix for display
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7
simpleCounter/Makefile
Normal file
7
simpleCounter/Makefile
Normal file
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@ -0,0 +1,7 @@
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build:
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yosys -m ghdl -p 'ghdl -fsynopsys leds.vhd ledmux.vhd matrixToSevenSeg.vhd -e leds; write_verilog leds.v; synth_ice40 -top leds -json leds.json'
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nextpnr-ice40 --hx8k --package cb132 --json leds.json --pcf leds.pcf --asc leds.asc
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icepack leds.asc leds.bin
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burn:
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iceFUNprog leds.bin
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72
simpleCounter/ledmux.vhd
Normal file
72
simpleCounter/ledmux.vhd
Normal file
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@ -0,0 +1,72 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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entity ledmux is
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port(
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clock : in std_logic;
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reset_n : in std_logic;
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leds0 : in std_logic_vector(7 downto 0);
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leds1 : in std_logic_vector(7 downto 0);
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leds2 : in std_logic_vector(7 downto 0);
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leds3 : in std_logic_vector(7 downto 0);
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ledRow : out std_logic_vector(7 downto 0);
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ledCol : out std_logic_vector(3 downto 0)
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);
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end entity ledmux;
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architecture arch of ledmux is
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signal counter : std_logic_vector(12 downto 0);
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begin
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syncCounter : process(clock) begin
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if(rising_edge(clock))then
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if(reset_n = '0') then
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counter <= (others => '0');
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else
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counter <= counter + "0000000000001";
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end if;
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end if;
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end process;
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muxCol : process (clock) begin
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if (reset_n = '0') then
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ledCol <= "0000";
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else
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case counter(12 downto 11) is
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when "00" =>
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ledCol <= "1110";
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when "01" =>
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ledCol <= "1101";
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when "10" =>
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ledCol <= "1011";
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when "11" =>
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ledCol <= "0111";
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when others =>
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ledCol <= "1111";
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end case;
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end if;
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end process;
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muxScan : process(clock) begin
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if (reset_n = '0') then
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ledRow <= leds0;
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else
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case counter(12 downto 11) is
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when "00" =>
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ledRow <= leds0;
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when "01" =>
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ledRow <= leds1;
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when "10" =>
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ledRow <= leds2;
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when "11" =>
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ledRow <= leds3;
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when others =>
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ledRow <= leds0;
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end case;
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end if;
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end process;
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end arch;
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21580
simpleCounter/leds.asc
Normal file
21580
simpleCounter/leds.asc
Normal file
File diff suppressed because it is too large
Load diff
BIN
simpleCounter/leds.bin
Normal file
BIN
simpleCounter/leds.bin
Normal file
Binary file not shown.
14275
simpleCounter/leds.json
Normal file
14275
simpleCounter/leds.json
Normal file
File diff suppressed because it is too large
Load diff
19
simpleCounter/leds.pcf
Normal file
19
simpleCounter/leds.pcf
Normal file
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# For iceFUN board
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set_io --warn-no-port ledRow[0] C10
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set_io --warn-no-port ledRow[1] A10
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set_io --warn-no-port ledRow[2] D7
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set_io --warn-no-port ledRow[3] D6
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set_io --warn-no-port ledRow[4] A7
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set_io --warn-no-port ledRow[5] C7
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set_io --warn-no-port ledRow[6] A4
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set_io --warn-no-port ledRow[7] C4
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set_io --warn-no-port ledCol[0] A12
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set_io --warn-no-port ledCol[1] D10
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set_io --warn-no-port ledCol[2] A6
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set_io --warn-no-port ledCol[3] C5
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set_io --warn-no-port buttons[0] A5
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set_io --warn-no-port buttons[1] A11
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set_io --warn-no-port buttons[2] C6
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set_io --warn-no-port buttons[3] C11
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set_io --warn-no-port clock P7
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424
simpleCounter/leds.v
Normal file
424
simpleCounter/leds.v
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/* Generated by Yosys 0.33 (git sha1 2584903a060) */
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module ledmux(clock, reset_n, leds0, leds1, leds2, leds3, ledrow, ledcol);
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wire _00_;
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wire [12:0] _01_;
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wire [12:0] _02_;
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wire _03_;
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wire _04_;
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wire _05_;
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wire _06_;
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wire _07_;
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wire [3:0] _08_;
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wire [3:0] _09_;
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wire _10_;
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wire _11_;
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wire _12_;
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wire _13_;
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wire _14_;
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wire [7:0] _15_;
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wire [7:0] _16_;
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reg [12:0] _17_;
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input clock;
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wire clock;
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wire [12:0] counter;
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output [3:0] ledcol;
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wire [3:0] ledcol;
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output [7:0] ledrow;
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wire [7:0] ledrow;
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input [7:0] leds0;
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wire [7:0] leds0;
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input [7:0] leds1;
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wire [7:0] leds1;
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input [7:0] leds2;
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wire [7:0] leds2;
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input [7:0] leds3;
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wire [7:0] leds3;
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input reset_n;
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wire reset_n;
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assign _00_ = ~ reset_n;
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assign _01_ = counter + 13'h0001;
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assign _02_ = _00_ ? 13'h0000 : _01_;
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assign _03_ = ~ reset_n;
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assign _04_ = counter[12:11] == 2'h0;
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assign _05_ = counter[12:11] == 2'h1;
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assign _06_ = counter[12:11] == 2'h2;
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assign _07_ = counter[12:11] == 2'h3;
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function [3:0] \189 ;
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input [3:0] a;
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input [15:0] b;
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input [3:0] s;
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(* parallel_case *)
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casez (s)
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4'b???1:
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\189 = b[3:0];
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4'b??1?:
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\189 = b[7:4];
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4'b?1??:
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\189 = b[11:8];
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4'b1???:
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\189 = b[15:12];
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default:
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\189 = a;
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endcase
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endfunction
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assign _08_ = \189 (4'hf, 16'h7bde, { _07_, _06_, _05_, _04_ });
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assign _09_ = _03_ ? 4'h0 : _08_;
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assign _10_ = ~ reset_n;
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assign _11_ = counter[12:11] == 2'h0;
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assign _12_ = counter[12:11] == 2'h1;
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assign _13_ = counter[12:11] == 2'h2;
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assign _14_ = counter[12:11] == 2'h3;
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function [7:0] \205 ;
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input [7:0] a;
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input [31:0] b;
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input [3:0] s;
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(* parallel_case *)
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casez (s)
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4'b???1:
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\205 = b[7:0];
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4'b??1?:
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\205 = b[15:8];
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4'b?1??:
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\205 = b[23:16];
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4'b1???:
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\205 = b[31:24];
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default:
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\205 = a;
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endcase
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endfunction
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assign _15_ = \205 (leds0, { leds3, leds2, leds1, leds0 }, { _14_, _13_, _12_, _11_ });
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assign _16_ = _10_ ? leds0 : _15_;
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always @(posedge clock)
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_17_ <= _02_;
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assign counter = _17_;
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assign ledrow = _16_;
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assign ledcol = _09_;
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endmodule
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module leds(clock, buttons, ledRow, ledCol);
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wire _00_;
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reg [25:0] _01_;
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reg _02_;
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reg _03_;
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reg _04_;
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wire [25:0] _05_;
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wire [25:0] _06_;
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wire [7:0] _07_;
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wire [7:0] _08_;
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wire [7:0] _09_;
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wire [7:0] _10_;
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wire [7:0] _11_;
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wire [3:0] _12_;
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input [3:0] buttons;
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wire [3:0] buttons;
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input clock;
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wire clock;
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wire [7:0] \conv_inst:19 ;
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wire [7:0] \conv_inst:20 ;
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wire [7:0] \conv_inst:21 ;
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wire [7:0] \conv_inst:22 ;
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wire [25:0] counter;
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wire key0_d1;
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wire key0_d2;
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wire key0_d3;
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output [3:0] ledCol;
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wire [3:0] ledCol;
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output [7:0] ledRow;
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wire [7:0] ledRow;
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wire [3:0] ledrow_sig;
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wire [7:0] leds0_sig;
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wire [7:0] leds1_sig;
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wire [7:0] leds2_sig;
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wire [7:0] leds3_sig;
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wire [7:0] \mux_inst:31 ;
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wire [3:0] \mux_inst:32 ;
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wire reset_n;
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assign _00_ = ~ reset_n;
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assign _05_ = counter + 26'h0000001;
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assign _06_ = _00_ ? 26'h0000000 : _05_;
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always @(posedge clock)
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_01_ <= _06_;
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always @(posedge clock)
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_02_ <= buttons[0];
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always @(posedge clock)
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_03_ <= key0_d1;
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always @(posedge clock)
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_04_ <= key0_d2;
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matrixtosevenseg conv_inst (
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.clock(clock),
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.led0_out(_07_),
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.led1_out(_08_),
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.led2_out(_09_),
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.led3_out(_10_),
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.num_in(ledrow_sig),
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.reset_n(reset_n)
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);
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ledmux mux_inst (
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.clock(clock),
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.ledcol(_12_),
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.ledrow(_11_),
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.leds0(leds0_sig),
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.leds1(leds1_sig),
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.leds2(leds2_sig),
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.leds3(leds3_sig),
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.reset_n(reset_n)
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);
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assign counter = _01_;
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assign key0_d1 = _02_;
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assign key0_d2 = _03_;
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assign key0_d3 = _04_;
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assign reset_n = key0_d3;
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assign ledrow_sig = counter[25:22];
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assign leds0_sig = \conv_inst:19 ;
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assign leds1_sig = \conv_inst:20 ;
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assign leds2_sig = \conv_inst:21 ;
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assign leds3_sig = \conv_inst:22 ;
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assign \conv_inst:19 = _07_;
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assign \conv_inst:20 = _08_;
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assign \conv_inst:21 = _09_;
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assign \conv_inst:22 = _10_;
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assign \mux_inst:31 = _11_;
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assign \mux_inst:32 = _12_;
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assign ledRow = \mux_inst:31 ;
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assign ledCol = \mux_inst:32 ;
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endmodule
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module matrixtosevenseg(clock, reset_n, num_in, led0_out, led1_out, led2_out, led3_out);
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wire _00_;
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wire _01_;
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wire _02_;
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wire _03_;
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wire _04_;
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wire _05_;
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wire _06_;
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wire _07_;
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wire _08_;
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wire _09_;
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wire _10_;
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wire _11_;
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wire _12_;
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wire _13_;
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wire _14_;
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wire _15_;
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wire _16_;
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wire [7:0] _17_;
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wire [7:0] _18_;
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wire [7:0] _19_;
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wire [7:0] _20_;
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wire [7:0] _21_;
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wire [7:0] _22_;
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wire [7:0] _23_;
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wire [7:0] _24_;
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input clock;
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wire clock;
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output [7:0] led0_out;
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wire [7:0] led0_out;
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output [7:0] led1_out;
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wire [7:0] led1_out;
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output [7:0] led2_out;
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wire [7:0] led2_out;
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output [7:0] led3_out;
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wire [7:0] led3_out;
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input [3:0] num_in;
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wire [3:0] num_in;
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input reset_n;
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wire reset_n;
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function [7:0] \115 ;
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input [7:0] a;
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input [127:0] b;
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input [15:0] s;
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(* parallel_case *)
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casez (s)
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16'b???????????????1:
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\115 = b[7:0];
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16'b??????????????1?:
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\115 = b[15:8];
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16'b?????????????1??:
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\115 = b[23:16];
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16'b????????????1???:
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\115 = b[31:24];
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16'b???????????1????:
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\115 = b[39:32];
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16'b??????????1?????:
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\115 = b[47:40];
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16'b?????????1??????:
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\115 = b[55:48];
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16'b????????1???????:
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\115 = b[63:56];
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16'b???????1????????:
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\115 = b[71:64];
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16'b??????1?????????:
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\115 = b[79:72];
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16'b?????1??????????:
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\115 = b[87:80];
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16'b????1???????????:
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\115 = b[95:88];
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16'b???1????????????:
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\115 = b[103:96];
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16'b??1?????????????:
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\115 = b[111:104];
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16'b?1??????????????:
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\115 = b[119:112];
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16'b1???????????????:
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\115 = b[127:120];
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default:
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\115 = a;
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endcase
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endfunction
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assign _18_ = \115 (8'hff, 128'hf6767e7e77ee6e6efe6e6eef6e6eff7e, { _16_, _15_, _14_, _13_, _12_, _11_, _10_, _09_, _08_, _07_, _06_, _05_, _04_, _03_, _02_, _01_ });
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function [7:0] \133 ;
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input [7:0] a;
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input [127:0] b;
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input [15:0] s;
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(* parallel_case *)
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casez (s)
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16'b???????????????1:
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\133 = b[7:0];
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16'b??????????????1?:
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\133 = b[15:8];
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16'b?????????????1??:
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\133 = b[23:16];
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16'b????????????1???:
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\133 = b[31:24];
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16'b???????????1????:
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\133 = b[39:32];
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16'b??????????1?????:
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\133 = b[47:40];
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16'b?????????1??????:
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\133 = b[55:48];
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16'b????????1???????:
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\133 = b[63:56];
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16'b???????1????????:
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\133 = b[71:64];
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16'b??????1?????????:
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\133 = b[79:72];
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16'b?????1??????????:
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\133 = b[87:80];
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16'b????1???????????:
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\133 = b[95:88];
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16'b???1????????????:
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\133 = b[103:96];
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16'b??1?????????????:
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\133 = b[111:104];
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16'b?1??????????????:
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\133 = b[119:112];
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16'b1???????????????:
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\133 = b[127:120];
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default:
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\133 = a;
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endcase
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endfunction
|
||||
assign _19_ = \133 (8'hff, 128'hf6767e7e77ee6e6efe6e6e006e6eff7e, { _16_, _15_, _14_, _13_, _12_, _11_, _10_, _09_, _08_, _07_, _06_, _05_, _04_, _03_, _02_, _01_ });
|
||||
function [7:0] \151 ;
|
||||
input [7:0] a;
|
||||
input [127:0] b;
|
||||
input [15:0] s;
|
||||
(* parallel_case *)
|
||||
casez (s)
|
||||
16'b???????????????1:
|
||||
\151 = b[7:0];
|
||||
16'b??????????????1?:
|
||||
\151 = b[15:8];
|
||||
16'b?????????????1??:
|
||||
\151 = b[23:16];
|
||||
16'b????????????1???:
|
||||
\151 = b[31:24];
|
||||
16'b???????????1????:
|
||||
\151 = b[39:32];
|
||||
16'b??????????1?????:
|
||||
\151 = b[47:40];
|
||||
16'b?????????1??????:
|
||||
\151 = b[55:48];
|
||||
16'b????????1???????:
|
||||
\151 = b[63:56];
|
||||
16'b???????1????????:
|
||||
\151 = b[71:64];
|
||||
16'b??????1?????????:
|
||||
\151 = b[79:72];
|
||||
16'b?????1??????????:
|
||||
\151 = b[87:80];
|
||||
16'b????1???????????:
|
||||
\151 = b[95:88];
|
||||
16'b???1????????????:
|
||||
\151 = b[103:96];
|
||||
16'b??1?????????????:
|
||||
\151 = b[111:104];
|
||||
16'b?1??????????????:
|
||||
\151 = b[119:112];
|
||||
16'b1???????????????:
|
||||
\151 = b[127:120];
|
||||
default:
|
||||
\151 = a;
|
||||
endcase
|
||||
endfunction
|
||||
assign _20_ = \151 (8'hff, 128'hfe7e817e8f019191009f0eef91710000, { _16_, _15_, _14_, _13_, _12_, _11_, _10_, _09_, _08_, _07_, _06_, _05_, _04_, _03_, _02_, _01_ });
|
||||
assign _21_ = _00_ ? 8'hff : _17_;
|
||||
assign _22_ = _00_ ? 8'hff : _18_;
|
||||
assign _23_ = _00_ ? 8'hff : _19_;
|
||||
assign _24_ = _00_ ? 8'hff : _20_;
|
||||
assign _00_ = ~ reset_n;
|
||||
assign _01_ = num_in == 4'h0;
|
||||
assign _02_ = num_in == 4'h1;
|
||||
assign _03_ = num_in == 4'h2;
|
||||
assign _04_ = num_in == 4'h3;
|
||||
assign _05_ = num_in == 4'h4;
|
||||
assign _06_ = num_in == 4'h5;
|
||||
assign _07_ = num_in == 4'h6;
|
||||
assign _08_ = num_in == 4'h7;
|
||||
assign _09_ = num_in == 4'h8;
|
||||
assign _10_ = num_in == 4'h9;
|
||||
assign _11_ = num_in == 4'ha;
|
||||
assign _12_ = num_in == 4'hb;
|
||||
assign _13_ = num_in == 4'hc;
|
||||
assign _14_ = num_in == 4'hd;
|
||||
assign _15_ = num_in == 4'he;
|
||||
assign _16_ = num_in == 4'hf;
|
||||
function [7:0] \97 ;
|
||||
input [7:0] a;
|
||||
input [127:0] b;
|
||||
input [15:0] s;
|
||||
(* parallel_case *)
|
||||
casez (s)
|
||||
16'b???????????????1:
|
||||
\97 = b[7:0];
|
||||
16'b??????????????1?:
|
||||
\97 = b[15:8];
|
||||
16'b?????????????1??:
|
||||
\97 = b[23:16];
|
||||
16'b????????????1???:
|
||||
\97 = b[31:24];
|
||||
16'b???????????1????:
|
||||
\97 = b[39:32];
|
||||
16'b??????????1?????:
|
||||
\97 = b[47:40];
|
||||
16'b?????????1??????:
|
||||
\97 = b[55:48];
|
||||
16'b????????1???????:
|
||||
\97 = b[63:56];
|
||||
16'b???????1????????:
|
||||
\97 = b[71:64];
|
||||
16'b??????1?????????:
|
||||
\97 = b[79:72];
|
||||
16'b?????1??????????:
|
||||
\97 = b[87:80];
|
||||
16'b????1???????????:
|
||||
\97 = b[95:88];
|
||||
16'b???1????????????:
|
||||
\97 = b[103:96];
|
||||
16'b??1?????????????:
|
||||
\97 = b[111:104];
|
||||
16'b?1??????????????:
|
||||
\97 = b[119:112];
|
||||
16'b1???????????????:
|
||||
\97 = b[127:120];
|
||||
default:
|
||||
\97 = a;
|
||||
endcase
|
||||
endfunction
|
||||
assign _17_ = \97 (8'hff, 128'h000000000001f191fe8171e0ff1dff00, { _16_, _15_, _14_, _13_, _12_, _11_, _10_, _09_, _08_, _07_, _06_, _05_, _04_, _03_, _02_, _01_ });
|
||||
assign led0_out = _21_;
|
||||
assign led1_out = _22_;
|
||||
assign led2_out = _23_;
|
||||
assign led3_out = _24_;
|
||||
endmodule
|
||||
99
simpleCounter/leds.vhd
Normal file
99
simpleCounter/leds.vhd
Normal file
|
|
@ -0,0 +1,99 @@
|
|||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity leds is
|
||||
port(
|
||||
clock : in std_logic;
|
||||
buttons : in std_logic_vector(3 downto 0);
|
||||
ledRow : out std_logic_vector(7 downto 0);
|
||||
ledCol : out std_logic_vector(3 downto 0)
|
||||
);
|
||||
end entity leds;
|
||||
|
||||
architecture arch of leds is
|
||||
|
||||
component ledmux is
|
||||
port(
|
||||
clock : in std_logic;
|
||||
reset_n : in std_logic;
|
||||
leds0 : in std_logic_vector(7 downto 0);
|
||||
leds1 : in std_logic_vector(7 downto 0);
|
||||
leds2 : in std_logic_vector(7 downto 0);
|
||||
leds3 : in std_logic_vector(7 downto 0);
|
||||
ledRow : out std_logic_vector(7 downto 0);
|
||||
ledCol : out std_logic_vector(3 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
component matrixToSevenSeg is
|
||||
port(
|
||||
clock : in std_logic;
|
||||
reset_n : in std_logic;
|
||||
num_in : in std_logic_vector(3 downto 0);
|
||||
led0_out : out std_logic_vector(7 downto 0);
|
||||
led1_out : out std_logic_vector(7 downto 0);
|
||||
led2_out : out std_logic_vector(7 downto 0);
|
||||
led3_out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
signal counter : std_logic_vector(25 downto 0);
|
||||
signal key0_d1 : std_logic;
|
||||
signal key0_d2 : std_logic;
|
||||
signal key0_d3 : std_logic;
|
||||
signal reset_n : std_logic;
|
||||
signal ledRow_sig : std_logic_vector(3 downto 0);
|
||||
signal leds0_sig : std_logic_vector(7 downto 0);
|
||||
signal leds1_sig : std_logic_vector(7 downto 0);
|
||||
signal leds2_sig : std_logic_vector(7 downto 0);
|
||||
signal leds3_sig : std_logic_vector(7 downto 0);
|
||||
begin
|
||||
|
||||
ledRow_sig <= counter(25 downto 22);
|
||||
|
||||
syncReset : process(clock) begin
|
||||
if (rising_edge(clock)) then
|
||||
key0_d1 <= buttons(0);
|
||||
key0_d2 <= key0_d1;
|
||||
key0_d3 <= key0_d2;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
reset_n <= key0_d3;
|
||||
|
||||
syncCounter : process (clock) begin
|
||||
if (rising_edge(clock)) then
|
||||
if (reset_n = '0') then
|
||||
counter <= "00" & x"000000";
|
||||
else
|
||||
counter <= counter + ("00" & x"000001");
|
||||
end if;
|
||||
end if;
|
||||
end process syncCounter;
|
||||
|
||||
conv_inst : component matrixToSevenSeg
|
||||
port map(
|
||||
clock => clock,
|
||||
reset_n => reset_n,
|
||||
num_in => ledRow_sig,
|
||||
led0_out => leds0_sig,
|
||||
led1_out => leds1_sig,
|
||||
led2_out => leds2_sig,
|
||||
led3_out => leds3_sig
|
||||
);
|
||||
|
||||
mux_inst : component ledmux
|
||||
port map(
|
||||
clock => clock,
|
||||
reset_n => reset_n,
|
||||
leds0 => leds0_sig,
|
||||
leds1 => leds1_sig,
|
||||
leds2 => leds2_sig,
|
||||
leds3 => leds3_sig,
|
||||
ledRow => ledRow,
|
||||
ledCol => ledCol
|
||||
);
|
||||
|
||||
end arch;
|
||||
119
simpleCounter/matrixToSevenSeg.vhd
Normal file
119
simpleCounter/matrixToSevenSeg.vhd
Normal file
|
|
@ -0,0 +1,119 @@
|
|||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity matrixToSevenSeg is
|
||||
port(
|
||||
clock : in std_logic;
|
||||
reset_n : in std_logic;
|
||||
num_in : in std_logic_vector(3 downto 0);
|
||||
led0_out : out std_logic_vector(7 downto 0);
|
||||
led1_out : out std_logic_vector(7 downto 0);
|
||||
led2_out : out std_logic_vector(7 downto 0);
|
||||
led3_out : out std_logic_vector(7 downto 0)
|
||||
);
|
||||
end entity matrixToSevenSeg;
|
||||
|
||||
architecture arch of matrixToSevenSeg is
|
||||
|
||||
begin
|
||||
|
||||
matrixConvert : process(clock) begin
|
||||
if ('0' = reset_n) then
|
||||
led0_out <= "11111111";
|
||||
led1_out <= "11111111";
|
||||
led2_out <= "11111111";
|
||||
led3_out <= "11111111";
|
||||
else
|
||||
case num_in is
|
||||
when "0000" => --0
|
||||
led0_out <= "00000000";
|
||||
led1_out <= "01111110";
|
||||
led2_out <= "01111110";
|
||||
led3_out <= "00000000";
|
||||
when "0001" => --1
|
||||
led0_out <= "11111111";
|
||||
led1_out <= "11111111";
|
||||
led2_out <= "11111111";
|
||||
led3_out <= "00000000";
|
||||
when "0010" => --2
|
||||
led0_out <= "00011101";
|
||||
led1_out <= "01101110";
|
||||
led2_out <= "01101110";
|
||||
led3_out <= "01110001";
|
||||
when "0011" => --3
|
||||
led0_out <= "11111111";
|
||||
led1_out <= "01101110";
|
||||
led2_out <= "01101110";
|
||||
led3_out <= "10010001";
|
||||
when "0100" => --4
|
||||
led0_out <= "11100000";
|
||||
led1_out <= "11101111";
|
||||
led2_out <= "00000000";
|
||||
led3_out <= "11101111";
|
||||
when "0101" => --5
|
||||
led0_out <= "01110001";
|
||||
led1_out <= "01101110";
|
||||
led2_out <= "01101110";
|
||||
led3_out <= "00001110";
|
||||
when "0110" => --6
|
||||
led0_out <= "10000001";
|
||||
led1_out <= "01101110";
|
||||
led2_out <= "01101110";
|
||||
led3_out <= "10011111";
|
||||
when "0111" => --7
|
||||
led0_out <= "11111110";
|
||||
led1_out <= "11111110";
|
||||
led2_out <= "11111110";
|
||||
led3_out <= "00000000";
|
||||
when "1000" => --8
|
||||
led0_out <= "10010001";
|
||||
led1_out <= "01101110";
|
||||
led2_out <= "01101110";
|
||||
led3_out <= "10010001";
|
||||
when "1001" => --9
|
||||
led0_out <= "11110001";
|
||||
led1_out <= "01101110";
|
||||
led2_out <= "01101110";
|
||||
led3_out <= "10010001";
|
||||
when "1010" => --A
|
||||
led0_out <= "00000001";
|
||||
led1_out <= "11101110";
|
||||
led2_out <= "11101110";
|
||||
led3_out <= "00000001";
|
||||
when "1011" => --B
|
||||
led0_out <= "00000000";
|
||||
led1_out <= "01110111";
|
||||
led2_out <= "01110111";
|
||||
led3_out <= "10001111";
|
||||
when "1100" => --C
|
||||
led0_out <= "00000000";
|
||||
led1_out <= "01111110";
|
||||
led2_out <= "01111110";
|
||||
led3_out <= "01111110";
|
||||
when "1101" => --D
|
||||
led0_out <= "00000000";
|
||||
led1_out <= "01111110";
|
||||
led2_out <= "01111110";
|
||||
led3_out <= "10000001";
|
||||
when "1110" => --E
|
||||
led0_out <= "00000000";
|
||||
led1_out <= "01110110";
|
||||
led2_out <= "01110110";
|
||||
led3_out <= "01111110";
|
||||
when "1111" => --F
|
||||
led0_out <= "00000000";
|
||||
led1_out <= "11110110";
|
||||
led2_out <= "11110110";
|
||||
led3_out <= "11111110";
|
||||
when others => --XXXX
|
||||
led0_out <= "11111111";
|
||||
led1_out <= "11111111";
|
||||
led2_out <= "11111111";
|
||||
led3_out <= "11111111";
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end arch;
|
||||
Loading…
Add table
Add a link
Reference in a new issue