blizzardfinnegan/icefunVHDL
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Tinkering with the iceFUN FPGA board, based on the iCE40-HX8K FPGA
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  • VHDL 85.5%
  • Makefile 14.5%
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Blizzard Finnegan d87a17c1e2
 Remove RISCV Core, move to separate repository
2024-11-04 21:58:06 -05:00
encryptionKeyGenerator Add timing analysis to makefiles 2024-10-30 10:03:03 -04:00
piezoBuzzer Add timing analysis to makefiles 2024-10-30 10:03:03 -04:00
simpleCounter Add timing analysis to makefiles 2024-10-30 10:03:03 -04:00
stopwatch Add timing analysis to makefiles 2024-10-30 10:03:03 -04:00
timer Add timing analysis to makefiles 2024-10-30 10:03:03 -04:00
.gitignore Add make files for subprojects 2024-10-26 16:14:48 -04:00
exampleOutput.txt Add timing analysis to makefiles 2024-10-30 10:03:03 -04:00
LICENSE Initial commit 2024-10-25 15:01:06 -04:00
Makefile Save working on the stopwatch 2024-10-26 21:02:47 -04:00
pinout.pcf Simple buzzer, start timer 2024-10-26 15:29:09 -04:00
README.md Init with first project 2024-10-25 15:27:15 -04:00

README.md

icefunVHDL

Tinkering with the iceFUN FPGA board, based on the iCE40-HX8K FPGA.

This work is loosely based on the provided code distributed at the DevanTech github repository. Since I'm not familiar with VHDL, this repository will be used to both write VHDL for the board, and slowly work my way up to learning Verliog.

Tools used:

At time of writing, iceFUNprog is necessary on my specific setup, as openFPGAloader erroneously claims unable to open ftdi device: -3 (device not found).

Currently working projects:

  • SimpleCounter: Counter using clock divider for input, and 8x4 LED matrix for display