3.9 KiB
DSC file
- unique platform GUID
- DSC spec should be identical
board .fdf definition is used for specifying information for building the flash image
SKU IDs: can have multiple SKUs for the same processor; not sure how it interacts though immediately
Include all packages in MdePkg/MdeLibs.dsc.inc (?)
Libs broken down further down
PCDs
[tbd]
Components
No graphic console available according to comments
Library descriptions
These are all the labeled unique and relevant libraries
JH7110DeviceTree
Platform/StarFive/JH7110Board/DeviceTree
Headers used for defining pin locations or similar, imported into dtsi files
Compile all C headers, then compile devicetree files
RiscVSpecialPlatformLib
struct fdt_match array; list of { .compatible = "brand,board-or-core" }
struct platform_override single object containing tlbr_flush_limit and fdt_fixup function pointers, along with above-listed match_table
special_platforms[] is a wrapper array for ^^
RiscVPlatformTimerLib
Platform/StarFive/Library
Assembly description for overriding timer mechanism for U5 series platform
li (Load immediate), ld (Load generic?) and return (function return stored in a0) calls; seems generic?
PeiCoreInfoHobLib
Exists both in Silicon/SiFive/U54/Library and Platforms/StarFive/JH7110/Library; compare?
Create core information Hands-Off-Blocks
Names itself as RiscVCoreplexInfoLib
Implements function BuildRiscVSmbiosHobs(). In this case, calls createcoreplexprocessorspecificdatahob, followed by createprocessorsmbiosdatahob, return success. These seem to be init programs, based on no (permanent) return value or feed in pointers. Might rely on build-time envvars or #define block.
Create Coreplex Processor Specific Data
Fed in unique id is 0
Get PCD pointer to PcdSiFiveU5MCCoreplexGuid. This is the ParentCoreGuid used later. Pcd vars are defined in Inf files
Get whether E5MCSupported. If it is supported, create a MC core using CreateU54E51CoreProcessorSpecificDataHob function; hartid 0, false for not-boot-hart, next param "true", pointer to externally-available GuidHobData, increment HartIdNumber
Iterate over remaining harts, calling the previously called function for each hart, then return success
Create Processor Smbios Data
Check if the pointer passed in is real; fail out
Call Createu54SmbiosType7L1DataHob function, passing param Uid and output pointer.
Call CreateU54SmbiosType4DataHob function
Build "SMBIOS Type 7 L2 cache record", following spec defined in PDF
assign data in SMBIOS Type 4 info, following spec
PlatformSecPpiLib
Platform/StarFive/Library
Provide PPI before PEI_CORE
2 functions: TemporaryRamMigration and TemporaryRamDone. Also return's platform SEC PPI before PEI Core
RiscVSpecialPlatformLib
Platform/StarFive/JH7110Board/Library
"Null library instance to provide platform override objects for RISCV", incorporates OpenSBIPlatform and OpenSBI
Fixes for sfence.vma by firtual address doesn't work, and S-mode software can't access PMP preotected region using 1GB Page table mapping
PciHostBridgeLib
Silicon/StarFive/HJ7110/Library
"Liberally borrowed from SynQuacer"
creates array objects based on information in MdeModulePkg/Include/Library/PciHostBridgeLib.h
PCI Segment Library
Silicon/StarFive/HJ7110/Library
PCI Segment Library; saw immediate comment "This PCIe config space is unusual".... oh dear
PCI devices are interfaced with through a lock.
Lots of aliased register read/write calls; PciSegmentReadBuffer and PciSegmentWriteBuffer seem to be the necessary calls
TimerDxe
Platform/StarFive/Universal/Dxe
RISC-V Timer Arch protocol module
CpuDxe
Silicon/RISC-V/Universal
RiscVSmbiosDxe
Silicon/RISC-V/Universal
SpiDxe
Silicon/StarFive/Driver
FvbDxe
Silicon/StarFive/Driver
SpiFlashDxe
Silicon/StarFive/Driver
FdtDxe
Silicon/RISC-V/Universal
PlatformPei
Platform/RISC-V/Universal
FdtPeim
Platform/RISC-V/Universal