INclude makefile
This commit is contained in:
parent
cf5643fa15
commit
8918668abd
GPG key ID:
61C1E13067E0018E
6 changed files with 34608 additions and 49 deletions
24
README.md
24
README.md
|
|
@ -1,5 +1,27 @@
|
|||
# RISC-V 32
|
||||
|
||||
An attempt at implementing a RISC-V 32-bit processor core
|
||||
An attempt at implementing a RISC-V 32-bit processor core, following the `RV32IMAFDCBZicsr_Zifencei_Ztso` extension set.
|
||||
|
||||
This expands to:
|
||||
- `RV32I` Integer base (not Embedded base)
|
||||
- `M` Multiply and Divide extension
|
||||
- `A` Atomic Operations
|
||||
- `F` single-precision Floating point operations
|
||||
- `D` Double-precision floating point operations
|
||||
- `C` Compressed instructions
|
||||
- `B` Binary operations extension
|
||||
- `Zicsr` Control and Status Register, and their operations
|
||||
- `Zifencei` Fence instruction
|
||||
- `Ztso` Total Store Ordering
|
||||
|
||||
Currently, all of the above are decoded, but none are processed.
|
||||
|
||||
For more information, see the repo's Wiki page.
|
||||
|
||||
The version of the RISC-V handbook in use can be found in the references folder.
|
||||
|
||||
Other projects helpful in the design of this project:
|
||||
- [Vortex General-Purpose GPU](https://github.com/vortexgpgpu/vortex)
|
||||
- Used for general microarchitecture guidance; 6-stage pipeline
|
||||
- [Domipheus' VHDL implementation of RISC-V](https://github.com/Domipheus/rpu)
|
||||
- Used for constants file. RPU implements `RV32IMZcsr`, while I intend to implement `RV32G`, that is, `RV32IMAFDZicsr_Zifencei`.
|
||||
|
|
|
|||
25
src/Makefile
Normal file
25
src/Makefile
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
PROJ = alu
|
||||
PCF = pinout.pcf
|
||||
FILES = alu.vhd constants.vhd
|
||||
BUILD=build
|
||||
|
||||
.PHONY: burn clean
|
||||
|
||||
cross: $(FILES)
|
||||
([ -d $(BUILD) ] || mkdir $(BUILD))
|
||||
yosys -m ghdl -p 'ghdl -fsynopsys $(FILES) -e $(PROJ); write_verilog $(BUILD)/$(PROJ).v'
|
||||
synth: | cross
|
||||
yosys -p 'synth_ice40 -top $(PROJ) -json $(BUILD)/$(PROJ).json' $(BUILD)/$(PROJ).v
|
||||
pnr: | synth
|
||||
nextpnr-ice40 --hx8k --package cb132 --json $(BUILD)/$(PROJ).json --pcf $(PCF) --asc $(BUILD)/$(PROJ).asc --pcf-allow-unconstrained
|
||||
timing: | pnr
|
||||
icetime -d hx8k -c 12 -r timingReport.txt -j $(BUILD)/timingReport.json $(BUILD)/$(PROJ).asc
|
||||
rtl: | cross
|
||||
yosys -p "prep -top $(PROJ); write_json $(BUILD)/$(PROJ).rtl.json" $(BUILD)/$(PROJ).v
|
||||
netlistsvg $(BUILD)/$(PROJ).rtl.json -o $(PROJ).svg
|
||||
burn: | pnr
|
||||
icepack $(BUILD)/$(PROJ).asc $(BUILD)/$(PROJ).bin
|
||||
iceFUNprog $(BUILD)/$(PROJ).bin
|
||||
|
||||
clean:
|
||||
rm -rf *.bin $(BUILD) timingReport.txt $(PROJ).svg
|
||||
34437
src/alu.json
Normal file
34437
src/alu.json
Normal file
File diff suppressed because one or more lines are too long
71
src/alu.vhd
71
src/alu.vhd
|
|
@ -3,32 +3,85 @@ USE ieee.std_logic_1164.ALL;
|
|||
USE ieee.std_logic_unsigned.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
library riscv32;
|
||||
USE riscv32.constants.ALL;
|
||||
library work;
|
||||
USE work.constants.ALL;
|
||||
|
||||
|
||||
ENTITY alu IS
|
||||
PORT(
|
||||
-- Inputs
|
||||
clk : IN STD_LOGIC;
|
||||
--opimm_op is converted to opcode outside
|
||||
op_flag : IN STD_LOGIC;
|
||||
opcode : IN STD_LOGIC_VECTOR(OPCODE_LEN DOWNTO 0);
|
||||
opimm_flag : IN STD_LOGIC;
|
||||
opimm_op : IN STD_LOGIC_VECTOR(FUNCT3_LEN DOWNTO 0);
|
||||
opimm_imm : IN STD_LOGIC_VECTOR(IMM_I_LEN DOWNTO 0);
|
||||
reg1_addr : IN STD_LOGIC_VECTOR(REGLENM1 DOWNTO 0);
|
||||
reg1_val : IN STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
|
||||
reg2_addr : IN STD_LOGIC_VECTOR(REGLENM1 DOWNTO 0);
|
||||
--opimm_imm is converted to reg2_val
|
||||
reg2_val : IN STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
|
||||
dest_addr : IN STD_LOGIC_VECTOR(REGLENM1 DOWNTO 0);
|
||||
-- Outputs
|
||||
dest_val : OUT STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
|
||||
dest_val : OUT STD_LOGIC_VECTOR(XLENM1 DOWNTO 0)
|
||||
);
|
||||
END alu;
|
||||
|
||||
ARCHITECTURE rtl OF alu IS
|
||||
|
||||
SIGNAL add_out : STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
|
||||
SIGNAL sub_out : STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
|
||||
SIGNAL sll_out : STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
|
||||
SIGNAL slt_out : STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
|
||||
SIGNAL sltu_out: STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
|
||||
SIGNAL xor_out : STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
|
||||
SIGNAL srl_out : STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
|
||||
SIGNAL sra_out : STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
|
||||
SIGNAL or_out : STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
|
||||
SIGNAL and_out : STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
|
||||
SIGNAL shift_amt : STD_LOGIC_VECTOR(5 DOWNTO 0);
|
||||
|
||||
BEGIN
|
||||
|
||||
shift_amt <= reg2_val(5 DOWNTO 0);
|
||||
|
||||
--RV32I base
|
||||
add_out <= reg1_val + reg2_val;
|
||||
sub_out <= reg1_val - reg2_val;
|
||||
or_out <= reg1_val OR reg2_val;
|
||||
and_out <= reg1_val AND reg2_val;
|
||||
xor_out <= reg1_val XOR reg2_val;
|
||||
sll_out <= std_logic_vector(shift_left(unsigned(reg1_val), to_integer(unsigned(shift_amt))));
|
||||
srl_out <= std_logic_vector(shift_right(unsigned(reg1_val), to_integer(unsigned(shift_amt))));
|
||||
sra_out <= std_logic_vector(shift_right(signed(reg1_val), to_integer(unsigned(shift_amt))));
|
||||
sltu_out <= x"00000001" when unsigned(reg1_val) < unsigned(reg2_val) else x"00000000";
|
||||
slt_out <= x"00000001" when signed(reg1_val) < signed(reg2_val) else x"00000000";
|
||||
|
||||
--M extension
|
||||
--MUL
|
||||
--MULH
|
||||
--MULHSU
|
||||
--MULHU
|
||||
--DIV
|
||||
--DIVU
|
||||
--REM
|
||||
--REMU
|
||||
|
||||
mux : PROCESS(clk) BEGIN
|
||||
IF (rising_edge(clk)) THEN
|
||||
IF '0' = op_flag THEN
|
||||
dest_val <= (OTHERS => '0');
|
||||
ELSE
|
||||
CASE opcode IS
|
||||
WHEN OP_ADD => dest_val <= add_out;
|
||||
WHEN OP_SUB => dest_val <= sub_out;
|
||||
WHEN OP_SLL => dest_val <= sll_out;
|
||||
WHEN OP_SLT => dest_val <= slt_out;
|
||||
WHEN OP_SLTU=> dest_val <= sltu_out;
|
||||
WHEN OP_XOR => dest_val <= xor_out;
|
||||
WHEN OP_SRL => dest_val <= srl_out;
|
||||
WHEN OP_SRA => dest_val <= sra_out;
|
||||
WHEN OP_OR => dest_val <= or_out;
|
||||
WHEN OP_AND => dest_val <= and_out;
|
||||
WHEN OTHERS => dest_val <= (OTHERS => '0');
|
||||
END CASE;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
END rtl;
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@
|
|||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.all;
|
||||
|
||||
library riscv32;
|
||||
library work;
|
||||
package constants is
|
||||
|
||||
|
||||
|
|
@ -21,8 +21,8 @@ constant FLENM1 : integer := FLEN - 1;
|
|||
constant REGLEN : integer := 5;
|
||||
constant REGLENM1 : integer := REGLEN - 1;
|
||||
|
||||
constant ADDR_RESET: std_logic_vector(XLEN32M1 downto 0) := X"00000000";
|
||||
constant ADDR_INTVEC: std_logic_vector(XLEN32M1 downto 0) := X"00000100";
|
||||
constant ADDR_RESET: std_logic_vector(XLENM1 downto 0) := X"00000000";
|
||||
constant ADDR_INTVEC: std_logic_vector(XLENM1 downto 0) := X"00000100";
|
||||
|
||||
--Bitmasks
|
||||
CONSTANT WORD_MASK : STD_LOGIC_VECTOR(XLENM1 DOWNTO 0) := x"ffffffff";
|
||||
|
|
@ -49,15 +49,15 @@ constant RD_LEN : integer := RD_START - RD_END;
|
|||
|
||||
constant FUNCT3_START: integer := 14;
|
||||
constant FUNCT3_END: integer := 12;
|
||||
constant FUNCT3_LEN : integer := FUCNT3_START - FUNCT3_END;
|
||||
constant FUNCT3_LEN : integer := FUNCT3_START - FUNCT3_END;
|
||||
|
||||
constant R1_START: integer := 19;
|
||||
constant R1_END: integer := 15;
|
||||
constant R1_LEN = integer := R1_START - R1_END;
|
||||
constant R1_LEN : integer := R1_START - R1_END;
|
||||
|
||||
constant R2_START: integer := 24;
|
||||
constant R2_END: integer := 20;
|
||||
constant R2_LEN = integer := R2_START - R2_END;
|
||||
constant R2_LEN : integer := R2_START - R2_END;
|
||||
|
||||
constant FUNCT7_START: integer := 31;
|
||||
constant FUNCT7_END: integer := 25;
|
||||
|
|
@ -233,7 +233,7 @@ constant HFLOAT_INST : std_logic_vector(1 downto 0) := "10";
|
|||
constant FLOAT_OP_MADD : std_logic_vector(4 downto 0) := "00000";
|
||||
constant FLOAT_OP_MSUB : std_logic_vector(4 downto 0) := "00001";
|
||||
constant FLOAT_OP_NMSUB: std_logic_vector(4 downto 0) := "00010";
|
||||
constant FLOAT_OP_NMADD: std_logic_vector(4 downto 0) := "000l1";
|
||||
constant FLOAT_OP_NMADD: std_logic_vector(4 downto 0) := "00011";
|
||||
constant FLOAT_OP_ADD : std_logic_vector(4 downto 0) := "00100";
|
||||
constant FLOAT_OP_SUB : std_logic_vector(4 downto 0) := "00101";
|
||||
constant FLOAT_OP_MUL : std_logic_vector(4 downto 0) := "00110";
|
||||
|
|
@ -292,12 +292,12 @@ constant R1_FENCE : std_logic_vector(4 downto 0) := "00000";
|
|||
|
||||
constant F3_SYSTEM_ECALL: std_logic_vector(2 downto 0) := "000";
|
||||
constant IMM_I_SYSTEM_ECALL: std_logic_vector(11 downto 0) := "000000000000";
|
||||
constant IMM_U_ECALL : std_logic_vector(19 downto 0) := "0000000000000000000000000";
|
||||
constant IMM_U_ECALL : std_logic_vector(24 downto 0) := "0000000000000000000000000";
|
||||
constant F3_SYSTEM_EBREAK: std_logic_vector(2 downto 0) := "000";
|
||||
constant IMM_I_SYSTEM_EBREAK: std_logic_vector(11 downto 0) := "000000000001";
|
||||
constant IMM_U_EBREAK : std_logic_vector(19 downto 0) := "0000000000010000000000000";
|
||||
constant IMM_U_NTO : std_logic_vector(19 downto 0) := "0000000011010000000000000";
|
||||
constant IMM_U_STO : std_logic_vector(19 downto 0) := "0000000111010000000000000";
|
||||
constant IMM_U_EBREAK : std_logic_vector(24 downto 0) := "0000000000010000000000000";
|
||||
constant IMM_U_NTO : std_logic_vector(24 downto 0) := "0000000011010000000000000";
|
||||
constant IMM_U_STO : std_logic_vector(24 downto 0) := "0000000111010000000000000";
|
||||
constant F3_SYSTEM_CSRRW: std_logic_vector(2 downto 0) := "001";
|
||||
constant F3_SYSTEM_CSRRS: std_logic_vector(2 downto 0) := "010";
|
||||
constant F3_SYSTEM_CSRRC: std_logic_vector(2 downto 0) := "011";
|
||||
|
|
@ -319,35 +319,35 @@ constant R2_PRIV_RET: std_logic_vector(4 downto 0) := "00010";
|
|||
constant R2_PRIV_WFI: std_logic_vector(4 downto 0) := "00101";
|
||||
|
||||
|
||||
constant EXCEPTION_INT_USER_SOFTWARE: std_logic_vector(XLEN32M1 downto 0):= X"80000000";
|
||||
constant EXCEPTION_INT_SUPERVISOR_SOFTWARE: std_logic_vector(XLEN32M1 downto 0):= X"80000001";
|
||||
--constant EXCEPTION_INT_RESERVED: std_logic_vector(XLEN32M1 downto 0):= X"80000002";
|
||||
constant EXCEPTION_INT_MACHINE_SOFTWARE: std_logic_vector(XLEN32M1 downto 0):= X"80000003";
|
||||
constant EXCEPTION_INT_USER_TIMER: std_logic_vector(XLEN32M1 downto 0):= X"80000004";
|
||||
constant EXCEPTION_INT_SUPERVISOR_TIMER: std_logic_vector(XLEN32M1 downto 0):= X"80000005";
|
||||
--constant EXCEPTION_INT_RESERVED: std_logic_vector(XLEN32M1 downto 0):= X"80000006";
|
||||
constant EXCEPTION_INT_MACHINE_TIMER: std_logic_vector(XLEN32M1 downto 0):= X"80000007";
|
||||
constant EXCEPTION_INT_USER_EXTERNAL: std_logic_vector(XLEN32M1 downto 0):= X"80000008";
|
||||
constant EXCEPTION_INT_SUPERVISOR_EXTERNAL: std_logic_vector(XLEN32M1 downto 0):= X"80000009";
|
||||
--constant EXCEPTION_INT_RESERVED: std_logic_vector(XLEN32M1 downto 0):= X"8000000a";
|
||||
constant EXCEPTION_INT_MACHINE_EXTERNAL: std_logic_vector(XLEN32M1 downto 0):= X"8000000b";
|
||||
constant EXCEPTION_INT_USER_SOFTWARE: std_logic_vector(XLENM1 downto 0):= X"80000000";
|
||||
constant EXCEPTION_INT_SUPERVISOR_SOFTWARE: std_logic_vector(XLENM1 downto 0):= X"80000001";
|
||||
--constant EXCEPTION_INT_RESERVED: std_logic_vector(XLENM1 downto 0):= X"80000002";
|
||||
constant EXCEPTION_INT_MACHINE_SOFTWARE: std_logic_vector(XLENM1 downto 0):= X"80000003";
|
||||
constant EXCEPTION_INT_USER_TIMER: std_logic_vector(XLENM1 downto 0):= X"80000004";
|
||||
constant EXCEPTION_INT_SUPERVISOR_TIMER: std_logic_vector(XLENM1 downto 0):= X"80000005";
|
||||
--constant EXCEPTION_INT_RESERVED: std_logic_vector(XLENM1 downto 0):= X"80000006";
|
||||
constant EXCEPTION_INT_MACHINE_TIMER: std_logic_vector(XLENM1 downto 0):= X"80000007";
|
||||
constant EXCEPTION_INT_USER_EXTERNAL: std_logic_vector(XLENM1 downto 0):= X"80000008";
|
||||
constant EXCEPTION_INT_SUPERVISOR_EXTERNAL: std_logic_vector(XLENM1 downto 0):= X"80000009";
|
||||
--constant EXCEPTION_INT_RESERVED: std_logic_vector(XLENM1 downto 0):= X"8000000a";
|
||||
constant EXCEPTION_INT_MACHINE_EXTERNAL: std_logic_vector(XLENM1 downto 0):= X"8000000b";
|
||||
|
||||
constant EXCEPTION_INSTRUCTION_ADDR_MISALIGNED: std_logic_vector(XLEN32M1 downto 0):= X"00000000";
|
||||
constant EXCEPTION_INSTRUCTION_ACCESS_FAULT: std_logic_vector(XLEN32M1 downto 0):= X"00000001";
|
||||
constant EXCEPTION_INSTRUCTION_ILLEGAL: std_logic_vector(XLEN32M1 downto 0):= X"00000002";
|
||||
constant EXCEPTION_BREAKPOINT: std_logic_vector(XLEN32M1 downto 0):= X"00000003";
|
||||
constant EXCEPTION_LOAD_ADDRESS_MISALIGNED: std_logic_vector(XLEN32M1 downto 0):= X"00000004";
|
||||
constant EXCEPTION_LOAD_ACCESS_FAULT: std_logic_vector(XLEN32M1 downto 0):= X"00000005";
|
||||
constant EXCEPTION_STORE_AMO_ADDRESS_MISALIGNED:std_logic_vector(XLEN32M1 downto 0):= X"00000006";
|
||||
constant EXCEPTION_STORE_AMO_ACCESS_FAULT: std_logic_vector(XLEN32M1 downto 0):= X"00000007";
|
||||
constant EXCEPTION_ENVIRONMENT_CALL_FROM_UMODE: std_logic_vector(XLEN32M1 downto 0):= X"00000008";
|
||||
constant EXCEPTION_ENVIRONMENT_CALL_FROM_SMODE: std_logic_vector(XLEN32M1 downto 0):= X"00000009";
|
||||
--constant EXCEPTION_RESERVED: std_logic_vector(XLEN32M1 downto 0):= X"0000000a";
|
||||
constant EXCEPTION_ENVIRONMENT_CALL_FROM_MMODE: std_logic_vector(XLEN32M1 downto 0):= X"0000000b";
|
||||
constant EXCEPTION_INSTRUCTION_PAGE_FAULT: std_logic_vector(XLEN32M1 downto 0):= X"0000000c";
|
||||
constant EXCEPTION_LOAD_PAGE_FAULT: std_logic_vector(XLEN32M1 downto 0):= X"0000000d";
|
||||
--constant EXCEPTION_RESERVED: std_logic_vector(XLEN32M1 downto 0):= X"0000000e";
|
||||
constant EXCEPTION_STORE_AMO_PAGE_FAULT: std_logic_vector(XLEN32M1 downto 0):= X"0000000f";
|
||||
constant EXCEPTION_INSTRUCTION_ADDR_MISALIGNED: std_logic_vector(XLENM1 downto 0):= X"00000000";
|
||||
constant EXCEPTION_INSTRUCTION_ACCESS_FAULT: std_logic_vector(XLENM1 downto 0):= X"00000001";
|
||||
constant EXCEPTION_INSTRUCTION_ILLEGAL: std_logic_vector(XLENM1 downto 0):= X"00000002";
|
||||
constant EXCEPTION_BREAKPOINT: std_logic_vector(XLENM1 downto 0):= X"00000003";
|
||||
constant EXCEPTION_LOAD_ADDRESS_MISALIGNED: std_logic_vector(XLENM1 downto 0):= X"00000004";
|
||||
constant EXCEPTION_LOAD_ACCESS_FAULT: std_logic_vector(XLENM1 downto 0):= X"00000005";
|
||||
constant EXCEPTION_STORE_AMO_ADDRESS_MISALIGNED:std_logic_vector(XLENM1 downto 0):= X"00000006";
|
||||
constant EXCEPTION_STORE_AMO_ACCESS_FAULT: std_logic_vector(XLENM1 downto 0):= X"00000007";
|
||||
constant EXCEPTION_ENVIRONMENT_CALL_FROM_UMODE: std_logic_vector(XLENM1 downto 0):= X"00000008";
|
||||
constant EXCEPTION_ENVIRONMENT_CALL_FROM_SMODE: std_logic_vector(XLENM1 downto 0):= X"00000009";
|
||||
--constant EXCEPTION_RESERVED: std_logic_vector(XLENM1 downto 0):= X"0000000a";
|
||||
constant EXCEPTION_ENVIRONMENT_CALL_FROM_MMODE: std_logic_vector(XLENM1 downto 0):= X"0000000b";
|
||||
constant EXCEPTION_INSTRUCTION_PAGE_FAULT: std_logic_vector(XLENM1 downto 0):= X"0000000c";
|
||||
constant EXCEPTION_LOAD_PAGE_FAULT: std_logic_vector(XLENM1 downto 0):= X"0000000d";
|
||||
--constant EXCEPTION_RESERVED: std_logic_vector(XLENM1 downto 0):= X"0000000e";
|
||||
constant EXCEPTION_STORE_AMO_PAGE_FAULT: std_logic_vector(XLENM1 downto 0):= X"0000000f";
|
||||
|
||||
constant CSR_ADDR_PRIVILEGE_BIT_START: integer := 9;
|
||||
constant CSR_ADDR_PRIVILEGE_BIT_END: integer := 8;
|
||||
|
|
|
|||
22
src/pinout.pcf
Normal file
22
src/pinout.pcf
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
# For iceFUN board
|
||||
|
||||
set_io --warn-no-port ledRow[0] C10
|
||||
set_io --warn-no-port ledRow[1] A10
|
||||
set_io --warn-no-port ledRow[2] D7
|
||||
set_io --warn-no-port ledRow[3] D6
|
||||
set_io --warn-no-port ledRow[4] A7
|
||||
set_io --warn-no-port ledRow[5] C7
|
||||
set_io --warn-no-port ledRow[6] A4
|
||||
set_io --warn-no-port ledRow[7] C4
|
||||
set_io --warn-no-port ledCol[0] A12
|
||||
set_io --warn-no-port ledCol[1] D10
|
||||
set_io --warn-no-port ledCol[2] A6
|
||||
set_io --warn-no-port ledCol[3] C5
|
||||
set_io --warn-no-port buttons[0] A5
|
||||
set_io --warn-no-port buttons[1] A11
|
||||
set_io --warn-no-port buttons[2] C6
|
||||
set_io --warn-no-port buttons[3] C11
|
||||
set_io --warn-no-port speakerPos M12
|
||||
set_io --warn-no-port speakerMinus M6
|
||||
|
||||
set_io --warn-no-port clk P7
|
||||
Loading…
Add table
Reference in a new issue