An attempt at implementing a RISC-V 32-bit processor core
| references | ||
| src | ||
| LICENSE | ||
| README.md | ||
RISC-V 32
An attempt at implementing a RISC-V 32-bit processor core, following the RV32IMAFDCBZicsr_Zifencei_Ztso extension set.
This expands to:
- RV32I Integer base (not Embedded base)
- M Multiply and Divide extension
- A Atomic Operations
- F single-precision Floating point operations
- D Double-precision floating point operations
- C Compressed instructions
- B Binary operations extension
- Zicsr Control and Status Register, and their operations
- Zifencei Fence instruction
- Ztso Total Store Ordering
Currently, all of the above are decoded, but none are processed.
For more information, see the repo's Wiki page.
The version of the RISC-V handbook in use can be found in the references folder.
Other projects helpful in the design of this project:
- Vortex General-Purpose GPU
- Used for general microarchitecture guidance; 6-stage pipeline
- Domipheus' VHDL implementation of RISC-V
- Used for constants file. RPU implements
RV32IMZcsr, while I intend to implementRV32G, that is,RV32IMAFDZicsr_Zifencei.
- Used for constants file. RPU implements