Merge branch 'main' of ssh://git.blizzard.systems:25/blizzardfinnegan/riscv32
This commit is contained in:
commit
ec65e86ba0
GPG key ID:
61C1E13067E0018E
5 changed files with 88 additions and 42 deletions
48
src/alu.vhd
48
src/alu.vhd
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@ -6,24 +6,27 @@ USE ieee.numeric_std.ALL;
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library work;
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USE work.constants.ALL;
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-- Arithmetic Logic Unit
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-- Does not know how to deal with immediates, only raw values
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ENTITY alu IS
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PORT(
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-- Inputs
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-------------
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clk : IN STD_LOGIC;
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--opimm_op is converted to opcode outside
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op_flag : IN STD_LOGIC;
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op_enable : IN STD_LOGIC;
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opcode : IN STD_LOGIC_VECTOR(OPCODE_LEN DOWNTO 0);
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reg1_val : IN STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
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--opimm_imm is converted to reg2_val
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reg2_val : IN STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
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reg1_val : IN STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
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reg2_val : IN STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
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-- Outputs
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-------------
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dest_val : OUT STD_LOGIC_VECTOR(XLENM1 DOWNTO 0)
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);
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END alu;
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ARCHITECTURE rtl OF alu IS
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-- Internal signals, representing each calculation
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SIGNAL add_out : STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
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SIGNAL sub_out : STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
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SIGNAL sll_out : STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
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@ -47,6 +50,7 @@ SIGNAL rem_out : STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
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SIGNAL remu_out : STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
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SIGNAL shift_amt : STD_LOGIC_VECTOR(5 DOWNTO 0);
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-- Useful constants; 1, Unsigned and Signed max and min
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CONSTANT VAL_ONE : STD_LOGIC_VECTOR(XLENM1 DOWNTO 0) := x"00000001";
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CONSTANT VAL_UMAX : STD_LOGIC_VECTOR(XLENM1 DOWNTO 0) := (OTHERS => '1');
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CONSTANT VAL_UMIN : STD_LOGIC_VECTOR(XLENM1 DOWNTO 0) := (OTHERS => '0');
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@ -56,9 +60,12 @@ CONSTANT VAL_SMIN : STD_LOGIC_VECTOR(XLENM1 DOWNTO 0) := (XLENM1 => '1',OTHERS =
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BEGIN
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--Mask away extra shift values, since our inputs are register values rather than register addresses
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shift_amt <= reg2_val(5 DOWNTO 0);
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--RV32I base
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--RV32I base; +, -, ||, &&, XOR, Logical Shift Left (SLL), Logical shift right (SRL),
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-- arithmetic shift right (SRA), Set Less Than unsigned (SLTU), Set Less Than (SLT)
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-----------------------------
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add_out <= reg1_val + reg2_val;
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sub_out <= reg1_val - reg2_val;
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or_out <= reg1_val OR reg2_val;
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@ -70,19 +77,22 @@ sra_out <= std_logic_vector(shift_right(signed(reg1_val), to_integer(unsigned(sh
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sltu_out <= VAL_ONE when unsigned(reg1_val) < unsigned(reg2_val) else VAL_ZERO;
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slt_out <= VAL_ONE when signed(reg1_val) < signed(reg2_val) else VAL_ZERO;
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--M extension
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-----------------------------
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-- Pre-calculate for all sign variants
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raw_mul_uu <= std_logic_vector(unsigned(reg1_val) * unsigned(reg2_val));
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raw_mul_su <= std_logic_vector(signed(reg1_val) * unsigned(reg2_val));
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raw_mul_ss <= std_logic_vector(signed(reg1_val) * signed(reg2_val));
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--MUL
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--MUL (multiply)
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mul_out <= raw_mul_ss(XLENM1 DOWNTO 0);
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--MULH
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--MULH (Multiply High)
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mulh_out <= raw_mul_ss(XLENM1+XLEN DOWNTO XLEN);
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--MULHSU
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--MULHSU (Multiply High; Signed by unsigned)
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mulh_out <= raw_mul_su(XLENM1+XLEN DOWNTO XLEN);
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--MULHU
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--MULHU (Multiply High; unsigned)
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mulh_out <= raw_mul_uu(XLENM1+XLEN DOWNTO XLEN);
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--DIV
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--DIV (Divide)
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div : PROCESS(clk) BEGIN
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IF(VAL_UMIN = reg2_val) THEN
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div_out <= VAL_UMAX;
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@ -92,7 +102,7 @@ ELSE
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div_out <= std_logic_vector(signed(reg1_val) / signed(reg2_val));
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END IF;
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END PROCESS;
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--DIVU
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--DIVU (Divide unsigned)
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divu : PROCESS(clk) BEGIN
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IF(VAL_UMIN = reg2_val) THEN
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divu_out <= VAL_UMAX;
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@ -100,7 +110,7 @@ ELSE
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div_out <= std_logic_vector(unsigned(reg1_val) / unsigned(reg2_val));
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END IF;
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END PROCESS;
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--REM
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--REM (Remainder)
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rem_inst : PROCESS(clk) BEGIN
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IF(VAL_UMIN = reg2_val) THEN
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rem_out <= reg1_val;
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@ -109,7 +119,7 @@ ELSIF (VAL_SMAX = reg1_val AND VAL_UMAX = reg2_val) THEN
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ELSE
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rem_out <= std_logic_vector(signed(reg1_val) rem signed(reg2_val));
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END PROCESS;
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--REMU
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--REMU (Remainder unsigned)
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remu_inst : PROCESS(clk) BEGIN
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IF(VAL_UMIN = reg2_val) THEN
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remu_out <= VAL_UMIN;
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@ -118,11 +128,17 @@ ELSE
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END PROCESS;
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-- Output Implementation
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-----------------------------
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mux : PROCESS(clk) BEGIN
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IF (rising_edge(clk)) THEN
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IF '0' = op_flag THEN
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-- If we aren't supposed to be outputting a value, then don't
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IF '0' = op_enable THEN
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dest_val <= (OTHERS => '0');
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ELSE
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-- Check against internal opcode which calculation to output
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-- Not ideal, since multiplication/division is expensive compared
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-- to everything else, but this is a Proof of Concept
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CASE opcode IS
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WHEN OP_ADD => dest_val <= add_out;
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WHEN OP_SUB => dest_val <= sub_out;
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@ -8,24 +8,34 @@ USE riscv32.constants.ALL;
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-- TODO: Output should be 32-bit instruction fed into the inst. decoder
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-- Decoder of compressed instructions, as part of RVC (RISC-V Compressed instructions)
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-- All RCV instructions expand out to the base ISA, or the F/D extension's instructions
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-- This entity provides this expansion
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ENTITY compressed_decoder IS
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PORT(
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-- Inputs
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-------------
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instruction : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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clk : IN STD_LOGIC;
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reg_dest : OUT STD_LOGIC_VECTOR(REGLENM1 DOWNTO 0);
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reg1 : OUT STD_LOGIC_VECTOR(REGLENM1 DOWNTO 0);
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reg2 : OUT STD_LOGIC_VECTOR(REGLENM1 DOWNTO 0);
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-- Outputs
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-------------
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reg_dest : OUT STD_LOGIC_VECTOR(ADDR_WIDTHM1 DOWNTO 0);
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reg1 : OUT STD_LOGIC_VECTOR(ADDR_WIDTHM1 DOWNTO 0);
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reg2 : OUT STD_LOGIC_VECTOR(ADDR_WIDTHM1 DOWNTO 0);
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);
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END compressed_decoder;
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ARCHITECTURE behavioural OF compressed_decoder IS
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-- Compressed Instructions sometimes use a register width of 3 bits,
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-- Referred to in the official documentation as rs1', rs2', rd';
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-- Common notation translates this into the word "prime"
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CONSTANT REG_PRIME_LEN : integer := 3;
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CONSTANT ILLEGAL_INST : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
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CONSTANT REG_PRIME_LENM1 : integer := REG_PRIME_LEN - 1;
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-- Fields defined by the RVC spec
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SIGNAL major_op : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL r2_prime : STD_LOGIC_VECTOR(REG_PRIME_LENM1 DOWNTO 0);
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SIGNAL r1_prime : STD_LOGIC_VECTOR(REG_PRIME_LENM1 DOWNTO 0);
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@ -34,23 +44,25 @@ SIGNAL funct4 : STD_LOGIC_VECTOR(3 DOWNTO 0);
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SIGNAL funct3 : STD_LOGIC_VECTOR(2 DOWNTO 0);
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SIGNAL funct2 : STD_LOGIC_VECTOR(1 DOWNTO 0);
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SIGNAL reg_prime : STD_LOGIC_VECTOR(REG_PRIME_LENM1 DOWNTO 0);
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SIGNAL reg_decomp : STD_LOGIC_VECTOR(REGLENM1 DOWNTO 0);
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SIGNAL reg_decomp : STD_LOGIC_VECTOR(ADDR_WIDTHM1 DOWNTO 0);
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CONSTANT REG_CONVERT : STD_LOGIC_VECTOR(12 DOWNTO 0) := "000" & x"001";
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BEGIN
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-- See RISC-V Unprivileged ISA doc, Table 33 for definitions
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major_op <= instruction(1 DOWNTO 0);
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r2_prime <= instruction(4 DOWNTO 2);
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r1_prime <= instruction(9 DOWNTO 7);
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funct6 <= instruction(15 DOWNTO 10);
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funct4 <= instruction(15 DOWNTO 12);
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funct3 <= instruction(15 DOWNTO 13);
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funct2 <= instruciton(6 DOWNTO 5);
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funct2 <= instruction(6 DOWNTO 5);
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--Convert compressed register to standard:
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-- OR with x"0008"
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-- Convert compressed register to standard:
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-- Prepend the compressed register value with REG_CONVERT
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-- This corresponds 000 to Register x8/f8, 001 to x9/f9, etc
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compressed_inst : PROCESS(clk) BEGIN
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IF(rising_edge(clk)) THEN
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@ -61,9 +73,10 @@ IF(rising_edge(clk)) THEN
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END IF;
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CASE funct3 IS =>
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WHEN "000" =>
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--ADDI4SPN
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--ADDI4SPN (Add Immediate [multiplied by 4] to the x2, save to rd prime)
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addi_flag <= '1';
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reg_dest <= REG_CONVERT & r2_prime;
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reg1 <= x"002";
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addi_uimm <= instruction(10 DOWNTO 7) &
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instruction(12 DOWNTO 11) &
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instruction(5) &
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@ -17,6 +17,10 @@ constant XLENM1: integer := XLEN - 1;
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constant FLEN : integer := 32;
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constant FLENM1 : integer := FLEN - 1;
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-- Address width; used for defining an address vector
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CONSTANT ADDR_WIDTH : integer := 5;
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CONSTANT ADDR_WIDTHM1 : integer := ADDR_WIDTH - 1;
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constant ADDR_RESET: std_logic_vector(XLENM1 downto 0) := X"00000000";
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constant ADDR_INTVEC: std_logic_vector(XLENM1 downto 0) := X"00000100";
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@ -6,15 +6,16 @@ USE ieee.numeric_std.ALL;
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library riscv32;
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USE riscv32.constants.ALL;
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-- RV32G Instruction decoder
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ENTITY inst_decoder IS
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PORT(
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--**********************************************************
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--Inputs
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--**********************************************************
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instruction : IN STD_LOGIC_VECTOR(REGLENM1 DOWNTO 0);
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clk : IN STD_LOGIC;
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--**********************************************************
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--Outputs
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--
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--**********************************************************
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-- General use
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--These are wired to all outputs
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destination : OUT STD_LOGIC_VECTOR(REGLENM1 DOWNTO 0);
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@ -84,6 +85,7 @@ END inst_decoder;
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ARCHITECTURE behavioural OF inst_decoder IS
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-- See RISC-V Unprivileged ISA Documentation, section 2.3 for definitions
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SIGNAL op_code : STD_LOGIC_VECTOR(OPCODE_LEN DOWNTO 0);
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SIGNAL r_dest : STD_LOGIC_VECTOR(RD_LEN DOWNTO 0);
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SIGNAL funct3 : STD_LOGIC_VECTOR(FUNCT3_LEN DOWNTO 0);
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@ -98,11 +100,13 @@ SIGNAL imm_s : STD_LOGIC_VECTOR(IMM_S_LEN DOWNTO 0);
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SIGNAL imm_j : STD_LOGIC_VECTOR(IMM_J_LEN DOWNTO 0);
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SIGNAL imm_b : STD_LOGIC_VECTOR(IMM_B_LEN DOWNTO 0);
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SIGNAL funct4 : STD_LOGIC_VECTOR(FUNCT4_LEN DOWNTO 0);
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-- See definition in Unprivileged ISA doc, section 2.7
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SIGNAL fence_pred_sig: STD_LOGIC_VECTOR(FENCE_PRED_LEN DOWNTO 0);
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SIGNAL fence_succ_sig: STD_LOGIC_VECTOR(FENCE_SUCC_LEN DOWNTO 0);
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BEGIN
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--See Unpriv ISA doc, section 2.3
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op_code <= instruction(OPCODE_START DOWNTO OPCODE_END_2);
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r_dest <= instruction(RD_START DOWNTO RD_END);
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funct3 <= instruction(FUNCT3_START DOWNTO FUNCT3_END);
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@ -117,15 +121,15 @@ r3 <= instruction(R3_START DOWNTO R3_END);
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imm_i <= instruction(IMM_I_START DOWNTO IMM_I_END);
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imm_u <= instruction(IMM_U_START DOWNTO IMM_U_END);
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imm_s <= instruction(IMM_S_A_START DOWNTO IMM_S_A_END) & instruction(IMM_S_B_START DOWNTO IMM_S_B_END);
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--See Unpriv ISA doc, section 2.3
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imm_j <= instruction(31) & instruction(19 DOWNTO 12) & instruction(20) & instruction(30 DOWNTO 21);
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imm_b <= instruction(31) & instruction(7) & instruction(30 DOWNTO 25) & instruction(11 DOWNTO 8);
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--Export internal signals
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destination <= r_dest;
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reg1 <= r1;
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reg2 <= r2;
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-- Main behavioural block
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op_code_inst : PROCESS(clk) BEGIN
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IF (rising_edge(clk)) THEN
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--Set all flags to 0
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@ -141,11 +145,13 @@ op_code_inst : PROCESS(clk) BEGIN
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op_flag <= '0';
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flop_flag <= '0';
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hflop_flag<= '0';
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IF ("11" = instruction(1 downto 0)) THEN
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-- Opcodes must have the lowest 2 bits be '11'
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IF (NOT("11" = instruction(1 downto 0))) THEN
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invalid_inst <= '1';
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exit;
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END IF;
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-- Match to the correct op-code
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CASE op_code IS
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WHEN OPCODE_LOAD =>
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--Load to x reg
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@ -2,38 +2,45 @@ LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.ALL;
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USE ieee.numeric_std.ALL;
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USE ieee.math_real.all;
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library riscv32;
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USE riscv32.constants.ALL;
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-- Register file that reads from 2 addresses and writes to
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-- up to 1 address every clock; register 0 always returns 0
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-- Same implementation for both float and int, Length determines
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-- Which
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-- Same implementation for both float and int; REG_ADDR_WIDTH
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-- determines the address width, REG_DATA_WIDTH determines data width
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-- REG_COUNT;
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--
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-- This register file in it's current state is not efficiently compatible with any Bitmanip extensions
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ENTITY register_file IS
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GENERIC(
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LENGTH : INTEGER
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REG_ADDR_WIDTH : INTEGER := 5;
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REG_DATA_WIDTH : INTEGER := XLENM1;
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);
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PORT(
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-- INPUTS
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clk: IN STD_LOGIC;
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write_enable: IN STD_LOGIC;
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register_addr_a: IN STD_LOGIC_VECTOR(REGLENM1 DOWNTO 0);
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register_addr_b: IN STD_LOGIC_VECTOR(REGLENM1 DOWNTO 0);
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register_write_addr: IN STD_LOGIC_VECTOR(REGLENM1 DOWNTO 0);
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write_val: IN STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
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--Read addresses
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register_addr_a: IN STD_LOGIC_VECTOR(REG_ADDR_WIDTH DOWNTO 0);
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register_addr_b: IN STD_LOGIC_VECTOR(REG_ADDR_WIDTH DOWNTO 0);
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--Write address and value to write
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write_val: IN STD_LOGIC_VECTOR(REG_DATA_WIDTH DOWNTO 0);
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register_write_addr: IN STD_LOGIC_VECTOR(REG_ADDR_WIDTH DOWNTO 0);
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-- OUTPUTS
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register_a: OUT STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
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register_b: OUT STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
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register_a: OUT STD_LOGIC_VECTOR(REG_DATA_WIDTH DOWNTO 0);
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register_b: OUT STD_LOGIC_VECTOR(REG_DATA_WIDTH DOWNTO 0)
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);
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END integer_register_file;
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ARCHITECTURE behavioural OF integer_register_file IS
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TYPE register_t IS ARRAY(0 TO REGLENM1) OF STD_LOGIC_VECTOR(XLENM1 DOWNTO 0);
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TYPE register_t IS ARRAY(1 TO (2 ** REG_ADDR_WIDTH)) OF STD_LOGIC_VECTOR(REG_DATA_WIDTH DOWNTO 0);
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signal registers : register_t;
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CONSTANT reg_zero : STD_LOGIC_VECTOR(XLENM1 DOWNTO 0) := (OTHERS => '0');
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CONSTANT reg_zero : STD_LOGIC_VECTOR(REG_ADDR_WIDTH DOWNTO 0) := (OTHERS => '0');
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BEGIN
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