Table of Contents
This is a work-in-progress core based on the RISC-V ISA manual, version 20240411, whose HTML copies are embedded in this repo for convenience.
Pipeline stages
fetch branch-predict (later) decode pipeline bypass (later) execute write-back
Components
ALU
Register File
Register x0 is always tied to (OTHERS => '0').
Register x1 is generally reserved for return address.
Register x2 is generally reserved for stack pointer.
Register x5 is generally reserved as an alternate link register.
Instruction decoder
Instructions are aligned on a 4-byte boundary. Instruction address misaligned exception is generated on the taken branch or unconditional jump if the target address is not aligned properly.
ISA notes
The initial core will probably be RV32E (RISC-V 32-bit Embedded), which has 16 general purpose registers. This will be followed up by a RV32I (RISC-V 32-bit Integer) design, which is identical in all aspects except with 32 general purpose registers instead of 16. There may be an attempt at RV64E/RV64I in the future, but that will be in its own unique repository.