Fix bug in which OP decode previously went though the others=> case, which is now solely for invalid instructions. This caused an illegal intruction interrupt on all OP instructions (add,sub) or if interrupts are disabled, allowed the instruction to proceed without the data write from ALU occuring to the register file, causing major debug headaches.

vhdl/unit_decoder_RV32I.vhd

@@ -113,6 +113,11 @@ begin
 				 else
 					O_dataIMM <= X"0000" & "0000" & I_dataInst(IMM_I_START downto IMM_I_END);
 				 end if;
+			  
+              when OPCODE_OP =>
+                 O_int <= '0'; 
+                 O_regDwe <= '1';
+                 O_memOp <= "00000";
 			  when OPCODE_LOAD =>
 			     O_int <= '0'; 
 				 O_regDwe <= '1';