mirror of
https://github.com/Domipheus/RPU.git
synced 2025-04-18 19:15:13 -04:00
4b16f9bf6f
Updated ISA support to RV32IMZcsr - Passes riscv-compliance. Integer divide/rem in 34 cycles. Integer multiply in 2 cycles (when using xilinx dsp blocks!) Saved multiple cycles from fetch/memory load stages by short-cutting the start of memory requests. Compliant misaligned exceptions for jumps,loads and stores. Addrs starting 0xFxxxxxxx ignore alignment requests (assumes mmio space). Added CSRs for riscv-compliance requirements. Source ran through a formatter for ease of use.
289 lines
14 KiB
VHDL
289 lines
14 KiB
VHDL
----------------------------------------------------------------------------------
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-- Project Name: RISC-V CPU
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-- Description: Constants for instruction forms, opcodes, conditional flags, etc.
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--
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----------------------------------------------------------------------------------
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-- Copyright 2016 Colin Riley
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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package constants is
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constant XLEN: integer := 32;
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constant XLENM1: integer := XLEN - 1;
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constant XLEN32: integer:= 32;
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constant XLEN32M1: integer:= XLEN32 -1;
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constant BWIDTH: integer:= 32;
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constant BWIDTHM1: integer:= BWIDTH -1;
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constant ADDR_RESET: std_logic_vector(XLEN32M1 downto 0) := X"00000000";
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constant ADDR_INTVEC: std_logic_vector(XLEN32M1 downto 0) := X"00000100";
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-- PC unit opcodes
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constant PCU_OP_NOP: std_logic_vector(1 downto 0):= "00";
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constant PCU_OP_INC: std_logic_vector(1 downto 0):= "01";
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constant PCU_OP_ASSIGN: std_logic_vector(1 downto 0):= "10";
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constant PCU_OP_RESET: std_logic_vector(1 downto 0):= "11";
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-- Instruction Form Offsets
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constant OPCODE_START: integer := 6;
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constant OPCODE_END: integer := 0;
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constant OPCODE_END_2: integer := 2;
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constant RD_START: integer := 11;
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constant RD_END: integer := 7;
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constant FUNCT3_START: integer := 14;
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constant FUNCT3_END: integer := 12;
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constant R1_START: integer := 19;
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constant R1_END: integer := 15;
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constant R2_START: integer := 24;
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constant R2_END: integer := 20;
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constant FUNCT7_START: integer := 31;
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constant FUNCT7_END: integer := 25;
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constant IMM_I_START: integer := 31;
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constant IMM_I_END: integer := 20;
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constant IMM_U_START: integer := 31;
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constant IMM_U_END: integer := 12;
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constant IMM_S_A_START: integer := 31;
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constant IMM_S_A_END: integer := 25;
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constant IMM_S_B_START: integer := 11;
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constant IMM_S_B_END: integer := 7;
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-- Opcodes
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constant OPCODE_LOAD: std_logic_vector(4 downto 0) := "00000";
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constant OPCODE_STORE: std_logic_vector(4 downto 0) := "01000";
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constant OPCODE_MADD: std_logic_vector(4 downto 0) := "10000";
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constant OPCODE_BRANCH: std_logic_vector(4 downto 0) := "11000";
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constant OPCODE_JALR: std_logic_vector(4 downto 0) := "11001";
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constant OPCODE_JAL: std_logic_vector(4 downto 0) := "11011";
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constant OPCODE_SYSTEM: std_logic_vector(4 downto 0) := "11100";
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constant OPCODE_OP: std_logic_vector(4 downto 0) := "01100";
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constant OPCODE_OPIMM: std_logic_vector(4 downto 0) := "00100";
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constant OPCODE_MISCMEM: std_logic_vector(4 downto 0) := "00011";
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constant OPCODE_AUIPC: std_logic_vector(4 downto 0) := "00101";
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constant OPCODE_LUI: std_logic_vector(4 downto 0) := "01101";
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-- Flags
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constant F3_BRANCH_BEQ: std_logic_vector(2 downto 0) := "000";
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constant F3_BRANCH_BNE: std_logic_vector(2 downto 0) := "001";
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constant F3_BRANCH_BLT: std_logic_vector(2 downto 0) := "100";
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constant F3_BRANCH_BGE: std_logic_vector(2 downto 0) := "101";
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constant F3_BRANCH_BLTU: std_logic_vector(2 downto 0) := "110";
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constant F3_BRANCH_BGEU: std_logic_vector(2 downto 0) := "111";
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constant F3_JALR: std_logic_vector(2 downto 0) := "000";
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constant F3_LOAD_LB: std_logic_vector(2 downto 0) := "000";
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constant F3_LOAD_LH: std_logic_vector(2 downto 0) := "001";
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constant F3_LOAD_LW: std_logic_vector(2 downto 0) := "010";
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constant F3_LOAD_LBU: std_logic_vector(2 downto 0) := "100";
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constant F3_LOAD_LHU: std_logic_vector(2 downto 0) := "101";
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constant F2_MEM_LS_SIZE_B: std_logic_vector(1 downto 0) := "00";
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constant F2_MEM_LS_SIZE_H: std_logic_vector(1 downto 0) := "01";
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constant F2_MEM_LS_SIZE_W: std_logic_vector(1 downto 0) := "10";
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constant F3_STORE_SB: std_logic_vector(2 downto 0) := "000";
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constant F3_STORE_SH: std_logic_vector(2 downto 0) := "001";
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constant F3_STORE_SW: std_logic_vector(2 downto 0) := "010";
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constant F3_OPIMM_ADDI: std_logic_vector(2 downto 0) := "000";
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constant F3_OPIMM_SLTI: std_logic_vector(2 downto 0) := "010";
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constant F3_OPIMM_SLTIU: std_logic_vector(2 downto 0) := "011";
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constant F3_OPIMM_XORI: std_logic_vector(2 downto 0) := "100";
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constant F3_OPIMM_ORI: std_logic_vector(2 downto 0) := "110";
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constant F3_OPIMM_ANDI: std_logic_vector(2 downto 0) := "111";
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constant F3_OPIMM_SLLI: std_logic_vector(2 downto 0) := "001";
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constant F7_OPIMM_SLLI: std_logic_vector(6 downto 0) := "0000000";
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constant F3_OPIMM_SRLI: std_logic_vector(2 downto 0) := "101";
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constant F7_OPIMM_SRLI: std_logic_vector(6 downto 0) := "0000000";
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constant F3_OPIMM_SRAI: std_logic_vector(2 downto 0) := "101";
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constant F7_OPIMM_SRAI: std_logic_vector(6 downto 0) := "0100000";
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constant F3_OP_ADD: std_logic_vector(2 downto 0) := "000";
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constant F7_OP_ADD: std_logic_vector(6 downto 0) := "0000000";
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constant F3_OP_SUB: std_logic_vector(2 downto 0) := "000";
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constant F7_OP_SUB: std_logic_vector(6 downto 0) := "0100000";
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constant F3_OP_SLL: std_logic_vector(2 downto 0) := "001";
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constant F7_OP_SLL: std_logic_vector(6 downto 0) := "0000000";
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constant F3_OP_SLT: std_logic_vector(2 downto 0) := "010";
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constant F7_OP_SLT: std_logic_vector(6 downto 0) := "0000000";
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constant F3_OP_SLTU: std_logic_vector(2 downto 0) := "011";
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constant F7_OP_SLTU: std_logic_vector(6 downto 0) := "0000000";
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constant F3_OP_XOR: std_logic_vector(2 downto 0) := "100";
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constant F7_OP_XOR: std_logic_vector(6 downto 0) := "0000000";
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constant F3_OP_SRL: std_logic_vector(2 downto 0) := "101";
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constant F7_OP_SRL: std_logic_vector(6 downto 0) := "0000000";
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constant F3_OP_SRA: std_logic_vector(2 downto 0) := "101";
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constant F7_OP_SRA: std_logic_vector(6 downto 0) := "0100000";
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constant F3_OP_OR: std_logic_vector(2 downto 0) := "110";
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constant F7_OP_OR: std_logic_vector(6 downto 0) := "0000000";
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constant F3_OP_AND: std_logic_vector(2 downto 0) := "111";
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constant F7_OP_AND: std_logic_vector(6 downto 0) := "0000000";
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-- RV32M Extension
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constant F7_OP_M_EXT: std_logic_vector(6 downto 0) := "0000001";
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constant F3_OP_M_MUL: std_logic_vector(2 downto 0) := "000";
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constant F3_OP_M_MULH: std_logic_vector(2 downto 0) := "001";
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constant F3_OP_M_MULHSU: std_logic_vector(2 downto 0) := "010";
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constant F3_OP_M_MULHU: std_logic_vector(2 downto 0) := "011";
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constant F3_OP_M_DIV: std_logic_vector(2 downto 0) := "100";
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constant F3_OP_M_DIVU: std_logic_vector(2 downto 0) := "101";
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constant F3_OP_M_REM: std_logic_vector(2 downto 0) := "110";
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constant F3_OP_M_REMU: std_logic_vector(2 downto 0) := "111";
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-- bit 0 of the OP definitions denote unsigned ops; same as above
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constant ALU_INT32_DIV_OP_UNSIGNED_BIT: integer := 0;
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constant ALU_INT32_DIV_OP_DIV: std_logic_vector(1 downto 0) := "00";
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constant ALU_INT32_DIV_OP_DIVU: std_logic_vector(1 downto 0) := "01";
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constant ALU_INT32_DIV_OP_REM: std_logic_vector(1 downto 0) := "10";
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constant ALU_INT32_DIV_OP_REMU: std_logic_vector(1 downto 0) := "11";
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constant F3_MISCMEM_FENCE: std_logic_vector(2 downto 0) := "000";
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constant F3_MISCMEM_FENCEI: std_logic_vector(2 downto 0) := "001";
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constant F3_SYSTEM_ECALL: std_logic_vector(2 downto 0) := "000";
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constant IMM_I_SYSTEM_ECALL: std_logic_vector(11 downto 0) := "000000000000";
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constant F3_SYSTEM_EBREAK: std_logic_vector(2 downto 0) := "000";
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constant IMM_I_SYSTEM_EBREAK: std_logic_vector(11 downto 0) := "000000000001";
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constant F3_SYSTEM_CSRRW: std_logic_vector(2 downto 0) := "001";
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constant F3_SYSTEM_CSRRS: std_logic_vector(2 downto 0) := "010";
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constant F3_SYSTEM_CSRRC: std_logic_vector(2 downto 0) := "011";
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constant F3_SYSTEM_CSRRWI: std_logic_vector(2 downto 0) := "101";
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constant F3_SYSTEM_CSRRSI: std_logic_vector(2 downto 0) := "110";
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constant F3_SYSTEM_CSRRCI: std_logic_vector(2 downto 0) := "111";
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constant F3_PRIVOP: std_logic_vector(2 downto 0) := "000";
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constant F7_PRIVOP_URET: std_logic_vector(6 downto 0) := "0000000";
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constant F7_PRIVOP_SRET_WFI: std_logic_vector(6 downto 0) := "0001000";
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constant F7_PRIVOP_MRET: std_logic_vector(6 downto 0) := "0011000";
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constant F7_PRIVOP_SFENCE_VMA: std_logic_vector(6 downto 0) := "0001001";
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constant RD_PRIVOP: std_logic_vector(4 downto 0) := "00000";
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constant R2_PRIV_RET: std_logic_vector(4 downto 0) := "00010";
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constant R2_PRIV_WFI: std_logic_vector(4 downto 0) := "00101";
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constant EXCEPTION_INT_USER_SOFTWARE: std_logic_vector(XLEN32M1 downto 0):= X"80000000";
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constant EXCEPTION_INT_SUPERVISOR_SOFTWARE: std_logic_vector(XLEN32M1 downto 0):= X"80000001";
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--constant EXCEPTION_INT_RESERVED: std_logic_vector(XLEN32M1 downto 0):= X"80000002";
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constant EXCEPTION_INT_MACHINE_SOFTWARE: std_logic_vector(XLEN32M1 downto 0):= X"80000003";
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constant EXCEPTION_INT_USER_TIMER: std_logic_vector(XLEN32M1 downto 0):= X"80000004";
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constant EXCEPTION_INT_SUPERVISOR_TIMER: std_logic_vector(XLEN32M1 downto 0):= X"80000005";
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--constant EXCEPTION_INT_RESERVED: std_logic_vector(XLEN32M1 downto 0):= X"80000006";
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constant EXCEPTION_INT_MACHINE_TIMER: std_logic_vector(XLEN32M1 downto 0):= X"80000007";
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constant EXCEPTION_INT_USER_EXTERNAL: std_logic_vector(XLEN32M1 downto 0):= X"80000008";
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constant EXCEPTION_INT_SUPERVISOR_EXTERNAL: std_logic_vector(XLEN32M1 downto 0):= X"80000009";
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--constant EXCEPTION_INT_RESERVED: std_logic_vector(XLEN32M1 downto 0):= X"8000000a";
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constant EXCEPTION_INT_MACHINE_EXTERNAL: std_logic_vector(XLEN32M1 downto 0):= X"8000000b";
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constant EXCEPTION_INSTRUCTION_ADDR_MISALIGNED: std_logic_vector(XLEN32M1 downto 0):= X"00000000";
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constant EXCEPTION_INSTRUCTION_ACCESS_FAULT: std_logic_vector(XLEN32M1 downto 0):= X"00000001";
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constant EXCEPTION_INSTRUCTION_ILLEGAL: std_logic_vector(XLEN32M1 downto 0):= X"00000002";
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constant EXCEPTION_BREAKPOINT: std_logic_vector(XLEN32M1 downto 0):= X"00000003";
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constant EXCEPTION_LOAD_ADDRESS_MISALIGNED: std_logic_vector(XLEN32M1 downto 0):= X"00000004";
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constant EXCEPTION_LOAD_ACCESS_FAULT: std_logic_vector(XLEN32M1 downto 0):= X"00000005";
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constant EXCEPTION_STORE_AMO_ADDRESS_MISALIGNED:std_logic_vector(XLEN32M1 downto 0):= X"00000006";
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constant EXCEPTION_STORE_AMO_ACCESS_FAULT: std_logic_vector(XLEN32M1 downto 0):= X"00000007";
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constant EXCEPTION_ENVIRONMENT_CALL_FROM_UMODE: std_logic_vector(XLEN32M1 downto 0):= X"00000008";
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constant EXCEPTION_ENVIRONMENT_CALL_FROM_SMODE: std_logic_vector(XLEN32M1 downto 0):= X"00000009";
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--constant EXCEPTION_RESERVED: std_logic_vector(XLEN32M1 downto 0):= X"0000000a";
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constant EXCEPTION_ENVIRONMENT_CALL_FROM_MMODE: std_logic_vector(XLEN32M1 downto 0):= X"0000000b";
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constant EXCEPTION_INSTRUCTION_PAGE_FAULT: std_logic_vector(XLEN32M1 downto 0):= X"0000000c";
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constant EXCEPTION_LOAD_PAGE_FAULT: std_logic_vector(XLEN32M1 downto 0):= X"0000000d";
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--constant EXCEPTION_RESERVED: std_logic_vector(XLEN32M1 downto 0):= X"0000000e";
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constant EXCEPTION_STORE_AMO_PAGE_FAULT: std_logic_vector(XLEN32M1 downto 0):= X"0000000f";
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constant CSR_ADDR_PRIVILEGE_BIT_START: integer := 9;
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constant CSR_ADDR_PRIVILEGE_BIT_END: integer := 8;
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constant CSR_ADDR_PRIVILEGE_USER: std_logic_vector(1 downto 0):= "00";
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constant CSR_ADDR_PRIVILEGE_SUPERVISOR: std_logic_vector(1 downto 0):= "01";
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constant CSR_ADDR_PRIVILEGE_RESERVED: std_logic_vector(1 downto 0):= "10";
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constant CSR_ADDR_PRIVILEGE_MACHINE: std_logic_vector(1 downto 0):= "11";
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constant CSR_ADDR_ACCESS_BIT_START: integer := 11;
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constant CSR_ADDR_ACCESS_BIT_END: integer := 10;
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constant CSR_ADDR_ACCESS_READONLY: std_logic_vector(1 downto 0):= "11";
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-- CSR Opcodes:
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-- 0 - CSR Written
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-- 1 - CSR Read
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-- 2..3 0 operation
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-- 01 - read or write whole XLEN
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-- 10 - Set bits
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-- 11 - clear bits
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-- 4 - immediate or register
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constant CSR_OP_BITS_READ: integer := 0;
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constant CSR_OP_BITS_WRITTEN: integer := 1;
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constant CSR_OP_BITS_OPA: integer := 2;
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constant CSR_OP_BITS_OPB: integer := 3;
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constant CSR_OP_BITS_IMM: integer := 4;
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constant CSR_MAINOP_WR: std_logic_vector(1 downto 0) := "01";
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constant CSR_MAINOP_SET: std_logic_vector(1 downto 0) := "10";
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constant CSR_MAINOP_CLEAR: std_logic_vector(1 downto 0) := "11";
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constant CSR_OP_WR: std_logic_vector(4 downto 0) := "00100";
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constant CSR_OP_W: std_logic_vector(4 downto 0) := "00101";
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constant CSR_OP_R: std_logic_vector(4 downto 0) := "00110";
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constant CSR_OP_SET_WR: std_logic_vector(4 downto 0) := "01000";
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constant CSR_OP_SET_W: std_logic_vector(4 downto 0) := "01001";
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constant CSR_OP_SET_R: std_logic_vector(4 downto 0) := "01010";
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constant CSR_OP_CLEAR_WR: std_logic_vector(4 downto 0) := "01100";
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constant CSR_OP_CLEAR_W: std_logic_vector(4 downto 0) := "01101";
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constant CSR_OP_CLEAR_R: std_logic_vector(4 downto 0) := "01110";
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constant CSR_OP_IMM_WR: std_logic_vector(4 downto 0) := "10100";
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constant CSR_OP_IMM_W: std_logic_vector(4 downto 0) := "10101";
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constant CSR_OP_IMM_R: std_logic_vector(4 downto 0) := "10110";
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constant CSR_OP_IMM_SET_WR: std_logic_vector(4 downto 0) := "11000";
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constant CSR_OP_IMM_SET_W: std_logic_vector(4 downto 0) := "11001";
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constant CSR_OP_IMM_SET_R: std_logic_vector(4 downto 0) := "11010";
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constant CSR_OP_IMM_CLEAR_WR: std_logic_vector(4 downto 0) := "11100";
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constant CSR_OP_IMM_CLEAR_W: std_logic_vector(4 downto 0) := "11101";
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constant CSR_OP_IMM_CLEAR_R: std_logic_vector(4 downto 0) := "11110";
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end constants;
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package body constants is
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end constants;
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