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https://github.com/Domipheus/RPU.git
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4b16f9bf6f
Updated ISA support to RV32IMZcsr - Passes riscv-compliance. Integer divide/rem in 34 cycles. Integer multiply in 2 cycles (when using xilinx dsp blocks!) Saved multiple cycles from fetch/memory load stages by short-cutting the start of memory requests. Compliant misaligned exceptions for jumps,loads and stores. Addrs starting 0xFxxxxxxx ignore alignment requests (assumes mmio space). Added CSRs for riscv-compliance requirements. Source ran through a formatter for ease of use.
300 lines
No EOL
12 KiB
VHDL
300 lines
No EOL
12 KiB
VHDL
----------------------------------------------------------------------------------
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-- Project Name: RPU
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-- Description: control unit
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--
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----------------------------------------------------------------------------------
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-- Copyright 2016,2018,2019,2020 Colin Riley
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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library work;
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use work.constants.all;
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entity control_unit is
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port (
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I_clk : in STD_LOGIC;
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I_reset : in STD_LOGIC;
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I_halt : in STD_LOGIC;
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I_aluop : in STD_LOGIC_VECTOR (6 downto 0);
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-- interrupts
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I_int_enabled : in std_logic;
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I_int : in STD_LOGIC;
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O_int_ack : out STD_LOGIC;
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I_int_mem_data : in STD_LOGIC_VECTOR(XLENM1 downto 0);
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O_idata : out STD_LOGIC_VECTOR(XLENM1 downto 0);
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O_set_idata : out STD_LOGIC;
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O_set_ipc : out STD_LOGIC;
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O_set_irpc : out STD_LOGIC;
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O_instTick : out STD_LOGIC;
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-- mem controller state and control
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I_misalignment : in STD_LOGIC;
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I_ready : in STD_LOGIC;
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O_execute : out STD_LOGIC;
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I_dataReady : in STD_LOGIC;
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-- alu stall input
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I_aluWait : in STD_LOGIC;
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I_aluMultiCy : in STD_LOGIC;
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O_state : out STD_LOGIC_VECTOR (6 downto 0)
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);
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end control_unit;
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architecture Behavioral of control_unit is
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signal s_state : STD_LOGIC_VECTOR(6 downto 0) := "0000001";
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signal mem_ready : std_logic;
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signal mem_execute : std_logic := '0';
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signal mem_dataReady : std_logic;
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signal mem_cycles : integer := 0;
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signal next_s_state : STD_LOGIC_VECTOR(6 downto 0) := "0000001";
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signal interrupt_state : STD_LOGIC_VECTOR(2 downto 0) := "000";
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signal interrupt_ack : STD_LOGIC := '0';
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signal interrupt_was_inactive : STD_LOGIC := '1';
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signal set_idata : STD_LOGIC := '0';
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signal set_ipc : STD_LOGIC := '0';
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signal instTick : STD_LOGIC := '0';
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signal s_hasWaited : STD_LOGIC := '0';
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signal s_check_alignint : integer := 0;
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begin
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O_execute <= mem_execute;
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mem_ready <= I_ready;
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mem_dataReady <= I_dataReady;
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O_int_ack <= interrupt_ack;
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O_set_idata <= set_idata;
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O_set_irpc <= set_idata;
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O_set_ipc <= set_ipc;
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O_instTick <= instTick;
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process (I_clk)
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begin
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if rising_edge(I_clk) and I_halt = '0' then
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if I_reset = '1' then
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s_state <= "0000001";
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next_s_state <= "0000001";
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mem_cycles <= 0;
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mem_execute <= '0';
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interrupt_was_inactive <= '1';
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interrupt_ack <= '0';
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interrupt_state <= "000";
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set_ipc <= '0';
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O_idata <= X"00000000";
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set_idata <= '0';
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instTick <= '0';
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else
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case s_state is
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---------------------------
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-- FETCH
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when "0000001" => -- fetch
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if s_check_alignint /= 0 then
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-- If we've seen an alignment hint we need to stall here for s_check_alignint
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-- cycles, checking for an interrupt each time. When it's 0 we give up.
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if I_int_enabled = '1' and interrupt_was_inactive = '1' and I_int = '1' then
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interrupt_ack <= '1';
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interrupt_was_inactive <= '0';
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interrupt_state <= "001";
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next_s_state <= "0000001"; --F
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s_state <= "1000000"; --S
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s_check_alignint <= 0;
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else
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s_check_alignint <= s_check_alignint - 1;
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end if;
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else
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if I_int = '0' then
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interrupt_was_inactive <= '1';
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end if;
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instTick <= '0';
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if mem_cycles = 0 and mem_ready = '1' then
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mem_execute <= '1';
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mem_cycles <= 1;
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elsif mem_cycles = 1 then
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mem_execute <= '0';
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mem_cycles <= 2;
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elsif mem_cycles = 2 then
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mem_execute <= '0';
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if mem_dataReady = '1' then
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mem_cycles <= 0;
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s_state <= "0000010";
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end if;
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end if;
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end if;
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---------------------------
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-- DECODE
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when "0000010" => --- decode
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if I_int = '0' then
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interrupt_was_inactive <= '1';
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end if;
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s_hasWaited <= '0';
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s_state <= "0001000"; --E "0000100"; --R
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---------------------------
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-- EXECUTE
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when "0001000" => -- execute
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if I_int = '0' then
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interrupt_was_inactive <= '1';
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end if;
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--MEM/WB
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-- if it's not a memory alu op, goto writeback
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if (I_aluop(6 downto 2) = OPCODE_LOAD or
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I_aluop(6 downto 2) = OPCODE_STORE) then
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s_state <= "0010000"; -- MEM
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-- -- mem load short cut
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-- ISSUE - this fails to take into account the type of request, sizing, address correctly
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-- and therefore needs removed for compliance to pass.
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-- if I_misalignment = '0' and mem_cycles = 0 and mem_ready = '1' then
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-- mem_execute <= '1';
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-- mem_cycles <= 1;
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-- end if;
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else
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if I_aluWait = '0' then
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if I_aluMultiCy = '1' then
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if s_hasWaited = '1' then
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s_state <= "0100000"; -- WB
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end if;
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else
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s_state <= "0100000"; -- WB
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end if;
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s_hasWaited <= '1';
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end if;
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end if;
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---------------------------
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-- MEMORY
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when "0010000" => -- mem
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if I_int = '0' then
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interrupt_was_inactive <= '1';
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end if;
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-- alignment traps here are tricky.
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-- if we see the misalignment hint, wait 6 cycles and then test interrupt stall.
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-- if no interrupt we need to re-run the stage.
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if I_misalignment = '1' and s_check_alignint = 0 then
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s_check_alignint <= 6;
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elsif s_check_alignint > 0 then
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if I_int_enabled = '1' and interrupt_was_inactive = '1' and I_int = '1' then
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interrupt_ack <= '1';
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interrupt_was_inactive <= '0';
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interrupt_state <= "001";
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next_s_state <= "0000001"; --F
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s_state <= "1000000"; --F
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s_check_alignint <= 0;
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else
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s_check_alignint <= s_check_alignint - 1;
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end if;
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else
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if mem_cycles = 0 and mem_ready = '1' then
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mem_execute <= '1';
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mem_cycles <= 1;
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elsif mem_cycles = 1 then
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mem_execute <= '0';
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-- if it's a write, go through
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if I_aluop(6 downto 2) = OPCODE_STORE then
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mem_cycles <= 0;
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s_state <= "0100000"; -- WB
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elsif mem_dataReady = '1' then
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-- if read, wait for data
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mem_cycles <= 0;
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s_state <= "0100000"; -- WB
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end if;
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end if;
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end if;
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---------------------------
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-- WRITEBACK
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when "0100000" => -- writeback
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-- check interrupt?
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if I_int_enabled = '1' and interrupt_was_inactive = '1' and I_int = '1' then
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interrupt_ack <= '1';
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interrupt_was_inactive <= '0';
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interrupt_state <= "001";
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next_s_state <= "0000001"; --F
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s_state <= "1000000"; --F
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else
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if I_int = '0' then
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interrupt_was_inactive <= '1';
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end if;
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if I_misalignment = '1' and s_check_alignint = 0 then
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s_check_alignint <= 3;
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end if;
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-- misalign interrupts take a while to propagate
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-- this signal short cuts to ensure we can catch any misalignments before fetch.
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s_state <= "0000001"; --F
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-- if the mem system is ready, shortcut the fetch
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-- at this point, the next PC/Branch should be set.
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-- need to ensure the sizing is correct.
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if I_misalignment = '0' and mem_cycles = 0 and mem_ready = '1' then -- shortcut
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mem_execute <= '1'; -- shortcut
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mem_cycles <= 2; -- shortcut
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end if; -- shortcut
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end if;
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instTick <= '1';
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when "1000000" => -- stalls
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if I_int = '0' then
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interrupt_was_inactive <= '1';
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end if;
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instTick <= '0';
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-- interrupt stall
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if interrupt_state = "001" then
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-- give a cycle of latency
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-- set PC to interrupt vector.
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set_ipc <= '1';
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interrupt_state <= "101";
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elsif interrupt_state = "101" then
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set_ipc <= '0';
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interrupt_ack <= '0';
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interrupt_state <= "111";
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elsif interrupt_state = "111" then
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interrupt_state <= "000";
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s_state <= "0000001"; --F
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end if;
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when "1001000" =>
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-- alu 1 cycle stall
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s_state <= "0100000"; -- WB
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when others =>
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s_state <= "0000001";
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end case;
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end if;
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end if;
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end process;
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O_state <= s_state;
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end Behavioral; |