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https://github.com/Domipheus/RPU.git
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8803d1392d
Added Interrupt handling support: - Int enable masks - external interrupt - interrupt enable CSR - illegal instruction - system call instruction - breakpoints - interrupt CSR manipulation - correct nextPC resume/branch target selection Added debug data for CPU trace support Added vexrisc IRQ csrs for testing with 3rd party sw Added LINT unit locally arbitrates IRQs into priorities FIX: correctly sign extend data from memory controller FIX: set ALU to not branch on CSR unit ops FIX: correctly detect invalid operations in decode stage FIX: set signals not outputs in decode Change to use two regs arrays in register set to infer two port rams
63 lines
1.9 KiB
VHDL
63 lines
1.9 KiB
VHDL
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-- Project Name: RPU
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-- Description: Program Counter unit of RPU
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--
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-- Simple black box for holding and manipulating the PC
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--
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----------------------------------------------------------------------------------
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-- Copyright 2016,2018,2019,2020 Colin Riley
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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library work;
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use work.constants.all;
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entity pc_unit is
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Port (
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I_clk : in STD_LOGIC;
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I_nPC : in STD_LOGIC_VECTOR (XLENM1 downto 0);
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I_nPCop : in STD_LOGIC_VECTOR (1 downto 0);
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I_intVec: in STD_LOGIC;
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O_PC : out STD_LOGIC_VECTOR (XLENM1 downto 0)
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);
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end pc_unit;
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architecture Behavioral of pc_unit is
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signal current_pc: std_logic_vector( XLENM1 downto 0) := ADDR_RESET;
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begin
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process (I_clk)
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begin
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if rising_edge(I_clk) then
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case I_nPCop is
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when PCU_OP_NOP => -- NOP, keep PC the same/halt
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when PCU_OP_INC => -- increment
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current_pc <= std_logic_vector(unsigned(current_pc) + 4); -- 32bit byte addressing
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when PCU_OP_ASSIGN => -- set from external input
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current_pc <= I_nPC;
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when PCU_OP_RESET => -- Reset
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current_pc <= ADDR_RESET;
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when others =>
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end case;
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end if;
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end process;
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O_PC <= current_pc;
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end Behavioral;
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