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https://github.com/Domipheus/RPU.git
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4b16f9bf6f
Updated ISA support to RV32IMZcsr - Passes riscv-compliance. Integer divide/rem in 34 cycles. Integer multiply in 2 cycles (when using xilinx dsp blocks!) Saved multiple cycles from fetch/memory load stages by short-cutting the start of memory requests. Compliant misaligned exceptions for jumps,loads and stores. Addrs starting 0xFxxxxxxx ignore alignment requests (assumes mmio space). Added CSRs for riscv-compliance requirements. Source ran through a formatter for ease of use.
183 lines
No EOL
6.8 KiB
VHDL
183 lines
No EOL
6.8 KiB
VHDL
----------------------------------------------------------------------------------
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-- Project Name: RISC-V CPU
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-- Description: ALU unit for 32-bit integer division ops
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--
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----------------------------------------------------------------------------------
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-- Copyright 2020 Colin Riley
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.all;
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library work;
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use work.constants.all;
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entity alu_int32_div is
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port (
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I_clk : in STD_LOGIC;
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I_exec : in STD_LOGIC;
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I_dividend : in STD_LOGIC_VECTOR (XLEN32M1 downto 0);
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I_divisor : in STD_LOGIC_VECTOR (XLEN32M1 downto 0);
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I_op : in STD_LOGIC_VECTOR (1 downto 0);
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O_dataResult : out STD_LOGIC_VECTOR (XLEN32M1 downto 0);
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O_done : out STD_LOGIC;
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O_int : out std_logic
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);
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end alu_int32_div;
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architecture Behavioral of alu_int32_div is
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signal s_done : std_logic := '0';
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signal s_int : std_logic := '0';
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signal s_op : std_logic_vector(1 downto 0) := (others => '0');
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signal s_result : std_logic_vector(XLEN32M1 downto 0) := (others => '0');
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signal s_outsign : std_logic := '0';
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signal s_ur : unsigned(XLEN32M1 downto 0) := (others => '0');
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signal s_i : integer := 0;
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signal s_N : unsigned(XLEN32M1 downto 0) := (others => '0');
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signal s_D : unsigned(XLEN32M1 downto 0) := (others => '0');
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signal s_R : unsigned(XLEN32M1 downto 0) := (others => '0');
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signal s_Q : unsigned(XLEN32M1 downto 0) := (others => '0');
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constant STATE_IDLE : integer := 0;
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constant STATE_INFLIGHTU : integer := 1;
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constant STATE_COMPLETE : integer := 2;
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signal s_state : integer := 0;
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begin
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process (I_clk)
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begin
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if rising_edge(I_clk) then
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if s_state = STATE_IDLE then
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s_done <= '0';
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if I_exec = '1' then
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s_op <= I_op;
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s_done <= '0';
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if (I_divisor = X"00000000") then
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s_state <= STATE_COMPLETE;
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s_Q <= X"ffffffff";
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if I_dividend(31) = '1' then
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s_R <= unsigned(-signed(I_dividend));
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else
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s_R <= unsigned(I_dividend);
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end if;
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if (I_op = ALU_INT32_DIV_OP_DIV) or (I_op = ALU_INT32_DIV_OP_DIVU) then
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s_outsign <= '0';
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else
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s_outsign <= I_dividend(31);
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end if;
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elsif (I_divisor = X"00000001") and (I_op = ALU_INT32_DIV_OP_DIV) then
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s_state <= STATE_COMPLETE;
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s_R <= X"00000000";
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if I_dividend(31) = '1' then
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s_Q <= unsigned(-signed(I_dividend));
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else
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s_Q <= unsigned(I_dividend);
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end if;
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s_outsign <= I_dividend(31);
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else
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if I_op(ALU_INT32_DIV_OP_UNSIGNED_BIT) = '1' then
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s_state <= STATE_INFLIGHTU;
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s_N <= unsigned(I_dividend);
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s_D <= unsigned(I_divisor);
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s_ur <= X"00000000";
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s_Q <= X"00000000";
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s_R <= X"00000000";
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s_i <= 31;
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s_outsign <= '0';
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else
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s_state <= STATE_INFLIGHTU;
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if (I_op = ALU_INT32_DIV_OP_DIV) then
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s_outsign <= I_dividend(31) xor I_divisor(31);
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else
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s_outsign <= I_dividend(31);
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end if;
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if I_dividend(31) = '1' then
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s_N <= unsigned(-signed(I_dividend));
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else
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s_N <= unsigned(I_dividend);
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end if;
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if I_divisor(31) = '1' then
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s_D <= unsigned(-signed(I_divisor));
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else
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s_D <= unsigned(I_divisor);
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end if;
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s_ur <= X"00000000";
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s_Q <= X"00000000";
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s_R <= X"00000000";
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s_i <= 31;
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end if;
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end if;
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end if;
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elsif s_state = STATE_INFLIGHTU then
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-- binary integer long division loop
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if (s_R(30 downto 0) & s_N(s_i)) >= s_D then
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s_R <= (s_R(30 downto 0) & s_N(s_i)) - s_D;
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s_Q(s_i) <= '1';
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else
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s_R <= s_R(30 downto 0) & s_N(s_i);
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end if;
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if s_i = 0 then
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s_state <= STATE_COMPLETE;
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else
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s_i <= s_i - 1;
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end if;
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elsif s_state = STATE_COMPLETE then
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if (s_op = ALU_INT32_DIV_OP_DIV) or (s_op = ALU_INT32_DIV_OP_DIVU) then
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if (s_outsign = '1') then
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s_result <= std_logic_vector(-signed(std_logic_vector(s_Q)));
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else
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s_result <= std_logic_vector(s_Q);
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end if;
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else
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if (s_outsign = '1') then
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s_result <= std_logic_vector(-signed(std_logic_vector(s_R)));
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else
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s_result <= std_logic_vector(s_R);
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end if;
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end if;
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s_done <= '1';
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s_state <= STATE_IDLE;
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end if;
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end if;
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end process;
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O_dataResult <= s_result;
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O_done <= s_done;
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O_int <= s_int;
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end Behavioral; |