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https://github.com/Domipheus/RPU.git
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4b16f9bf6f
Updated ISA support to RV32IMZcsr - Passes riscv-compliance. Integer divide/rem in 34 cycles. Integer multiply in 2 cycles (when using xilinx dsp blocks!) Saved multiple cycles from fetch/memory load stages by short-cutting the start of memory requests. Compliant misaligned exceptions for jumps,loads and stores. Addrs starting 0xFxxxxxxx ignore alignment requests (assumes mmio space). Added CSRs for riscv-compliance requirements. Source ran through a formatter for ease of use.
116 lines
No EOL
4.1 KiB
VHDL
116 lines
No EOL
4.1 KiB
VHDL
----------------------------------------------------------------------------------
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-- Project Name: RISC-V CPU
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-- Description: Local Interrupt unit
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--
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----------------------------------------------------------------------------------
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-- Copyright 2018,2019,2020 Colin Riley
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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library work;
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use work.constants.all;
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entity lint_unit is
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port (
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I_clk : in STD_LOGIC;
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I_reset : in STD_LOGIC;
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I_nextPc : in STD_LOGIC_VECTOR (31 downto 0);
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I_pc : in STD_LOGIC_VECTOR (31 downto 0);
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I_enMask : in STD_LOGIC_VECTOR (3 downto 0);
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I_int0 : in STD_LOGIC;
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I_int_data0 : in STD_LOGIC_VECTOR (31 downto 0);
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O_int0_ack : out STD_LOGIC;
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I_int1 : in STD_LOGIC;
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I_int_data1 : in STD_LOGIC_VECTOR (31 downto 0);
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O_int1_ack : out STD_LOGIC;
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I_int2 : in STD_LOGIC;
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I_int_data2 : in STD_LOGIC_VECTOR (31 downto 0);
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O_int2_ack : out STD_LOGIC;
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I_int3 : in STD_LOGIC;
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I_int_data3 : in STD_LOGIC_VECTOR (31 downto 0);
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O_int3_ack : out STD_LOGIC;
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O_int : out STD_LOGIC;
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O_int_data : out STD_LOGIC_VECTOR (31 downto 0);
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O_int_epc : out STD_LOGIC_VECTOR (31 downto 0)
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);
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end lint_unit;
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architecture Behavioral of lint_unit is
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signal actual_int : std_logic := '0';
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signal actual_int_data : std_logic_vector (31 downto 0) := X"00000000";
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signal actual_int_epc : std_logic_vector (31 downto 0) := X"00000000";
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signal int0_ack : std_logic := '0';
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signal int1_ack : std_logic := '0';
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signal int2_ack : std_logic := '0';
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signal int3_ack : std_logic := '0';
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signal reset_counter : integer := 0;
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begin
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O_int <= actual_int;
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O_int_data <= actual_int_data;
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O_int_epc <= actual_int_epc;
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O_int0_ack <= int0_ack;
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O_int1_ack <= int1_ack;
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O_int2_ack <= int2_ack;
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O_int3_ack <= int3_ack;
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-- This simply filters one of the 4 int sources to a single one in
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-- decreasing priority, latching the data until a reset.
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arb : process (I_clk)
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begin
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if rising_edge(I_clk) then
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if I_reset = '1' then
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reset_counter <= 1;
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int0_ack <= '0';
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int1_ack <= '0';
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int2_ack <= '0';
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int3_ack <= '0';
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elsif reset_counter = 1 then
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reset_counter <= 2;
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elsif reset_counter = 2 then
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reset_counter <= 3;
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elsif reset_counter = 3 then
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actual_int <= '0';
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reset_counter <= 0;
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elsif reset_counter = 0 and actual_int = '0' then
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if I_enMask(0) = '1' and I_int0 = '1' and int0_ack = '0' then
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actual_int <= '1';
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actual_int_data <= I_int_data0;
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int0_ack <= '1';
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elsif I_enMask(1) = '1' and I_int1 = '1' and int1_ack = '0'then
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actual_int <= '1';
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actual_int_data <= I_int_data1;
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int1_ack <= '1';
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elsif I_enMask(2) = '1' and I_int2 = '1' and int2_ack = '0' then
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actual_int <= '1';
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actual_int_data <= I_int_data2;
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int2_ack <= '1';
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elsif I_enMask(3) = '1' and I_int3 = '1' and int3_ack = '0'then
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actual_int <= '1';
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actual_int_data <= I_int_data3;
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int3_ack <= '1';
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end if;
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end if;
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end if;
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end process;
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end Behavioral; |