mirror of
https://github.com/Domipheus/RPU.git
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4b16f9bf6f
Updated ISA support to RV32IMZcsr - Passes riscv-compliance. Integer divide/rem in 34 cycles. Integer multiply in 2 cycles (when using xilinx dsp blocks!) Saved multiple cycles from fetch/memory load stages by short-cutting the start of memory requests. Compliant misaligned exceptions for jumps,loads and stores. Addrs starting 0xFxxxxxxx ignore alignment requests (assumes mmio space). Added CSRs for riscv-compliance requirements. Source ran through a formatter for ease of use.
127 lines
No EOL
4.5 KiB
VHDL
127 lines
No EOL
4.5 KiB
VHDL
----------------------------------------------------------------------------------
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-- Project Name: RPU
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-- Description: Memory controller unit of RPU
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--
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-- Very simple. Allows for delays in reads, whilsts writes go through immediately.
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-- MEM_ signals are expected to be exposted to any SoC fabric.
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--
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----------------------------------------------------------------------------------
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-- Copyright 2016,2018,2019,2020 Colin Riley
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--
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-- Licensed under the Apache License, Version 2.0 (the "License");
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-- you may not use this file except in compliance with the License.
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-- You may obtain a copy of the License at
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--
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-- http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" BASIS,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.constants.all;
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entity mem_controller is
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port (
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I_clk : in STD_LOGIC;
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I_reset : in STD_LOGIC;
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O_ready : out STD_LOGIC;
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I_execute : in STD_LOGIC;
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I_dataWe : in STD_LOGIC;
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I_address : in STD_LOGIC_VECTOR (XLENM1 downto 0);
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I_data : in STD_LOGIC_VECTOR (XLENM1 downto 0);
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I_dataByteEn : in STD_LOGIC_VECTOR(1 downto 0);
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I_signExtend : in STD_LOGIC;
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O_data : out STD_LOGIC_VECTOR (XLENM1 downto 0);
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O_dataReady : out STD_LOGIC;
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MEM_I_ready : in STD_LOGIC;
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MEM_O_cmd : out STD_LOGIC;
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MEM_O_we : out STD_LOGIC;
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MEM_O_byteEnable : out STD_LOGIC_VECTOR (1 downto 0);
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MEM_O_addr : out STD_LOGIC_VECTOR (XLENM1 downto 0);
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MEM_O_data : out STD_LOGIC_VECTOR (XLENM1 downto 0);
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MEM_I_data : in STD_LOGIC_VECTOR (XLENM1 downto 0);
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MEM_I_dataReady : in STD_LOGIC
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);
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end mem_controller;
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architecture Behavioral of mem_controller is
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signal we : std_logic := '0';
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signal addr : STD_LOGIC_VECTOR (XLENM1 downto 0) := X"00000000";
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signal indata : STD_LOGIC_VECTOR (XLENM1 downto 0) := X"00000000";
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signal outdata : STD_LOGIC_VECTOR (XLENM1 downto 0) := X"00000000";
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signal byteEnable : STD_LOGIC_VECTOR (1 downto 0) := "11";
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signal cmd : STD_LOGIC := '0';
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signal state : integer := 0;
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signal ready : STD_LOGIC := '0';
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begin
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process (I_clk, I_execute)
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begin
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if rising_edge(I_clk) then
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if I_reset = '1' then
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we <= '0';
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cmd <= '0';
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state <= 0;
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O_dataReady <= '0';
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elsif state = 0 and I_execute = '1' and MEM_I_ready = '1' then
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we <= I_dataWe;
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addr <= I_address;
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indata <= I_data;
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byteEnable <= I_dataByteEn;
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cmd <= '1';
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O_dataReady <= '0';
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outdata <= X"ABCDEFEE";
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if I_dataWe = '0' then
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state <= 1;-- read
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else
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state <= 2;-- write
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end if;
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elsif state = 1 then
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cmd <= '0';
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if MEM_I_dataReady = '1' then
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O_dataReady <= '1';
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-- sign extend, if required
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if I_signExtend = '1' then
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if I_dataByteEn = F2_MEM_LS_SIZE_W then
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outdata <= MEM_I_data;
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elsif I_dataByteEn = F2_MEM_LS_SIZE_H then
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outdata <= std_logic_vector(resize(signed(MEM_I_data(15 downto 0)), XLEN));
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elsif I_dataByteEn = F2_MEM_LS_SIZE_B then
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outdata <= std_logic_vector(resize(signed(MEM_I_data(7 downto 0)), XLEN));
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end if;
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else
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outdata <= MEM_I_data;
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end if;
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state <= 2;
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end if;
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elsif state = 2 then
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cmd <= '0';
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state <= 0;
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O_dataReady <= '0';
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end if;
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end if;
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end process;
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O_data <= outdata;
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O_ready <= (MEM_I_ready and not I_execute) when state = 0 else '0';
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MEM_O_cmd <= cmd;
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MEM_O_byteEnable <= byteEnable;
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MEM_O_data <= indata;
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MEM_O_addr <= addr;
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MEM_O_we <= we;
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end Behavioral; |