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Colin Riley 4b16f9bf6f RPU 1.0 
Updated ISA support to RV32IMZcsr - Passes riscv-compliance.
Integer divide/rem in 34 cycles.
Integer multiply in 2 cycles (when using xilinx dsp blocks!)
Saved multiple cycles from fetch/memory load stages by short-cutting the start of memory requests.
Compliant misaligned exceptions for jumps,loads and stores. Addrs starting 0xFxxxxxxx ignore alignment requests (assumes mmio space).
Added CSRs for riscv-compliance requirements.
Source ran through a formatter for ease of use.
2020-09-11 00:06:01 +01:00
..
alu_int32_div.vhd RPU 1.0 2020-09-11 00:06:01 +01:00
constants.vhd RPU 1.0 2020-09-11 00:06:01 +01:00
control_unit.vhd RPU 1.0 2020-09-11 00:06:01 +01:00
core.vhd RPU 1.0 2020-09-11 00:06:01 +01:00
csr_unit.vhd RPU 1.0 2020-09-11 00:06:01 +01:00
lint_unit.vhd RPU 1.0 2020-09-11 00:06:01 +01:00
mem_controller.vhd RPU 1.0 2020-09-11 00:06:01 +01:00
pc_unit.vhd Core can now boot Zephyr RTOS 2020-05-17 23:39:17 +01:00
register_set.vhd Core can now boot Zephyr RTOS 2020-05-17 23:39:17 +01:00
unit_alu_RV32_I.vhd RPU 1.0 2020-09-11 00:06:01 +01:00
unit_decoder_RV32I.vhd RPU 1.0 2020-09-11 00:06:01 +01:00