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Changing branch second cycle
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lcbcFoo
parent
ebd2e0f821
commit
09614d73b0
3 changed files with 50 additions and 63 deletions
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@ -97,16 +97,8 @@
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* Integer unit
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*/
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#define CONFIG_IU_NWINDOWS (8)
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#define CONFIG_IU_V8MULDIV 1
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#undef CONFIG_IU_MUL_LATENCY_2
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#undef CONFIG_IU_MUL_LATENCY_4
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#define CONFIG_IU_MUL_LATENCY_5 1
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#undef CONFIG_IU_MUL_MAC
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#define CONFIG_IU_MUL_INFERRED 1
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#undef CONFIG_IU_MUL_MODGEN
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#undef CONFIG_IU_MUL_TECHSPEC
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#undef CONFIG_IU_MUL_DW
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#define CONFIG_IU_BP 1
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#undef CONFIG_IU_V8MULDIV
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#undef CONFIG_IU_BP
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#undef CONFIG_IU_SVT
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#define CONFIG_IU_LDELAY (1)
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#define CONFIG_IU_WATCHPOINTS (0)
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@ -1,15 +1,9 @@
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-----------------------------------------------------------------------------
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-- LEON3 Demonstration design test bench configuration
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-- Copyright (C) 2009 Aeroflex Gaisler
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------------------------------------------------------------------------------
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library techmap;
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use techmap.gencomp.all;
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package config is
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-- Technology and synthesis options
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constant CFG_FABTECH : integer := artix7;
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@ -32,9 +26,9 @@ package config is
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constant CFG_LEON3 : integer := 1;
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constant CFG_NCPU : integer := (1);
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constant CFG_NWIN : integer := (8);
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constant CFG_V8 : integer := 2 + 4*0;
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constant CFG_V8 : integer := 0 + 4*0;
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constant CFG_MAC : integer := 0;
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constant CFG_BP : integer := 1;
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constant CFG_BP : integer := 0;
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constant CFG_SVT : integer := 0;
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constant CFG_RSTADDR : integer := 16#00000#;
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constant CFG_LDDEL : integer := (1);
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@ -149,19 +143,12 @@ package config is
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constant CFG_GRETH : integer := 1;
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constant CFG_GRETH1G : integer := 0;
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constant CFG_ETH_FIFO : integer := 8;
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-- UART 1
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constant CFG_UART1_ENABLE : integer := 1;
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constant CFG_UART1_FIFO : integer := 1;
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-- LEON3 interrupt controller
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constant CFG_IRQ3_ENABLE : integer := 1;
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constant CFG_IRQ3_NSEC : integer := 0;
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-- Modular timer
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constant CFG_GPT_ENABLE : integer := 1;
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constant CFG_GPT_NTIM : integer := (2);
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@ -171,12 +158,10 @@ package config is
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constant CFG_GPT_SEPIRQ : integer := 1;
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constant CFG_GPT_WDOGEN : integer := 0;
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constant CFG_GPT_WDOG : integer := 16#0#;
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-- GPIO port
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constant CFG_GRGPIO_ENABLE : integer := 1;
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constant CFG_GRGPIO_IMASK : integer := 16#0000#;
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constant CFG_GRGPIO_WIDTH : integer := (8);
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-- SPI memory controller
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constant CFG_SPIMCTRL : integer := 1;
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constant CFG_SPIMCTRL_SDCARD : integer := 0;
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@ -187,7 +172,6 @@ package config is
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constant CFG_SPIMCTRL_ASCALER : integer := (2);
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constant CFG_SPIMCTRL_PWRUPCNT : integer := (0);
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constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
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-- Dynamic Partial Reconfiguration
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constant CFG_PRC : integer := 0;
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constant CFG_CRC_EN : integer := 0;
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@ -195,7 +179,6 @@ package config is
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constant CFG_WORDS_BLOCK : integer := 100;
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constant CFG_DCM_FIFO : integer := 0;
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constant CFG_DPR_FIFO : integer := 9;
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-- GRLIB debugging
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constant CFG_DUART : integer := 1;
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end;
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@ -1480,7 +1480,7 @@ architecture rtl of iu3 is
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when others => null;
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end case;
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--tmp(31 downto 2) := "010000000000000000000000000100";
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tmp(31 downto 2) := addr(31 downto 2) + pc(31 downto 2);
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tmp(31 downto 2) := addr(31 downto 2) + pc(31 downto 2) + 1;
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return (tmp);
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end;
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@ -1915,7 +1915,11 @@ end;
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ex_bpmiss, ra_bpannul : out std_logic) is
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variable miss : std_logic;
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begin
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miss := (not r.e.ctrl.annul) and r.e.bp and not branch_true(icc, r.e.ctrl.inst);
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if(r.e.ctrl.inst(6 downto 0) = R_BRANCH) and (r.e.ctrl.cnt = "01") then
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miss := (not r.e.ctrl.annul) and r.e.bp and not branch_true(icc, r.e.ctrl.inst);
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else
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miss := '0';
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end if;
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--ra_bpannul := miss and r.e.ctrl.inst(29);
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ra_bpannul := miss;
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ex_bpmiss := miss;
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@ -1970,7 +1974,6 @@ end;
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when R_BRANCH =>
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if r.d.cnt = "01" then
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nobp := BPRED;
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icc_check_bp := '1';
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end if;
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when R_LD | R_ST =>
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@ -2001,8 +2004,8 @@ end;
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chkmul := chkmul or divinsn;
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end if;
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bicc_hold := icc_check and not icc_valid(r);
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bicc_hold_bp := icc_check_bp and not icc_valid(r);
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bicc_hold := icc_check; --and not icc_valid(r);
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bicc_hold_bp := icc_check_bp; --and not icc_valid(r);
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if (((r.a.ctrl.ld or chkmul) and r.a.ctrl.wreg and ldchkra) = '1') and
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(((ldcheck1 = '1') and (r.a.ctrl.rd = rfa1)) or
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@ -2086,12 +2089,12 @@ end;
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when R_BRANCH =>
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if r.d.cnt = "01" then
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branch := branch_true;
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de_jmpl := branch_true;
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if hold_pc = '0' then
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if (branch = '1') then
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if (annul = '1') then
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if (de_jmpl = '1') then
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--if (annul = '1') then
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annul_next := '1';
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end if;
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--end if;
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else
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annul_next := annul_next or annul;
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end if;
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@ -2124,18 +2127,18 @@ end;
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cnt := r.d.cnt; annul_next := '0'; pv := '1';
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end if;
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hold_pc := (hold_pc or ldlock) and not annul_all;
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if icbpmiss='1' and r.d.annul='0' then
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annul_current := '1'; annul_next := '1'; pv := '0'; hold_pc := '0';
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end if;
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if ((exbpmiss and r.a.ctrl.annul and r.d.pv and not hold_pc) = '1') then
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annul_next := '1'; pv := '0';
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end if;
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if ((exbpmiss and not r.a.ctrl.annul and r.d.pv) = '1') then
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annul_next := '1'; pv := '0'; annul_current := '1';
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end if;
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if ((exbpmiss and not r.a.ctrl.annul and not r.d.pv and not hold_pc) = '1') then
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annul_next := '1'; pv := '0';
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end if;
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-- if icbpmiss='1' and r.d.annul='0' then
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-- annul_current := '1'; annul_next := '1'; pv := '0'; hold_pc := '0';
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-- end if;
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-- if ((exbpmiss and r.a.ctrl.annul and r.d.pv and not hold_pc) = '1') then
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-- annul_next := '1'; pv := '0';
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-- end if;
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-- if ((exbpmiss and not r.a.ctrl.annul and r.d.pv) = '1') then
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-- annul_next := '1'; pv := '0'; annul_current := '1';
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-- end if;
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-- if ((exbpmiss and not r.a.ctrl.annul and not r.d.pv and not hold_pc) = '1') then
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-- annul_next := '1'; pv := '0';
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-- end if;
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if irqlat/=0 and r.d.irqstart='1' and r.d.irqlatmet='0' then
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annul_current := '1';
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@ -3653,12 +3656,18 @@ begin
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dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load, v.m.casa);
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-- RV32I change
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if(r.e.alusel = EXE_RES_ADD) then --
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if(r.e.ctrl.inst(6 downto 0) = R_BRANCH) then -- BRANCH
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ex_jump_address := branch_address(r.e.ctrl.inst, r.e.ctrl.pc(31 downto PCLOW), de_rexbaddr1, r.d.rexen);
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--ex_jump_address := x"000002" & "00";
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elsif(r.e.alusel = EXE_RES_ADD) then -- JALR
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ex_jump_address := ex_add_res(32 downto PCLOW+1);
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--ex_jump_address := x"4000003" & "00";
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else -- JAL
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ex_jump_address := ex_add_res(32 downto PCLOW+1) + r.e.ctrl.pc(31 downto PCLOW);
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--ex_jump_address := x"4000004" & "00";
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end if;
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logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
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ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
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misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, xc_wimmask, ex_misc_res, ex_edata);
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@ -3697,7 +3706,7 @@ begin
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if (DBGUNIT and (r.x.rstate = dsu2)) then v.m.ctrl.ld := '1'; end if;
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dci.eaddress <= ex_add_res(32 downto 1);
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dci.edata <= ex_edata2;
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bp_miss_ex(r, r.m.icc, ex_bpmiss, ra_bpannul);
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--bp_miss_ex(r, r.m.icc, ex_bpmiss, ra_bpannul);
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v.m .itrhit := r.e.itrhit;
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@ -3732,7 +3741,7 @@ begin
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v.e.ymsb, v.e.mul, ra_div, v.e.mulstep, v.e.mac, v.e.ldbp2, v.e.invop2
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);
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cin_gen(r, v.m.icc(0), v.e.alucin);
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bp_miss_ra(r, ra_bpmiss, de_bpannul);
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--bp_miss_ra(r, ra_bpmiss, de_bpannul);
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v.e.bp := r.a.bp and not ra_bpmiss;
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@ -3936,19 +3945,22 @@ begin
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v.f.pc := ex_jump_address; v.f.branch := '1';
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npc := v.f.pc;
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end if;
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elsif (ex_jump and not bpmiss) = '1' then
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elsif ex_jump = '1' then
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v.f.pc := ex_jump_address; v.f.branch := '1';
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npc := v.f.pc;
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elsif (((ico.bpmiss and not r.d.annul) or r.a.bpimiss) and not bpmiss) = '1' then
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v.f.pc := r.d.pc; v.f.branch := '1';
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npc := v.f.pc;
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v.a.bpimiss := ico.bpmiss and not r.d.annul;
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elsif (de_branch and not bpmiss) = '1'
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then
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v.f.pc := branch_address(de_inst, de_pcout(31 downto PCLOW), de_rexbaddr1, r.d.rexen); v.f.branch := '1';
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npc := v.f.pc;
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-- elsif (ex_jump and not bpmiss) = '1' then
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-- v.f.pc := ex_jump_address; v.f.branch := '1';
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-- npc := v.f.pc;
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-- elsif (((ico.bpmiss and not r.d.annul) or r.a.bpimiss) and not bpmiss) = '1' then
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-- v.f.pc := r.d.pc; v.f.branch := '1';
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-- npc := v.f.pc;
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-- v.a.bpimiss := ico.bpmiss and not r.d.annul;
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-- elsif de_branch = '1'
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-- then
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-- v.f.pc := branch_address(de_inst, de_pcout(31 downto PCLOW), de_rexbaddr1, r.d.rexen); v.f.branch := '1';
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-- npc := v.f.pc;
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else
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v.f.branch := bpmiss; v.f.pc := fe_npc; npc := v.f.pc;
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v.f.branch := '0'; v.f.pc := fe_npc; npc := v.f.pc;
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end if;
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ici.dpc <= r.d.pc(31 downto 2) & "00";
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