Merge branch 'master' of https://github.com/lcbcFoo/riscv-leon

README.md

@@ -24,14 +24,14 @@ Also, we wanted to show to the hardware developers community that it is possible
 
 ---
 ## <a name="repo-map"></a> Repository Map
-The directories `bin`, `boards` and `software` where simply copied from GRLIB and contain scripts, templates and small programs used by GRLIB. The directory `doc` constains the documentation from GRLIB (may be updated with ReonV specific documentation on future). Directory `designs` contains all scripts and configuration designs for each specific FPGA board supported by Leon3 (and by ReonV). Directory `lib` constains the source code of the processor and of all peripherals or IP cores provided by GRLIB, the 7-stage integer pipeline changed to RISC-V is at `lib/gaisler/leon3v3/iu4.vhd`. Lastly, `riscv` contains scripts and configuration files to run a test example on ReonV (check [Running an Example[(#running) section). 
+The directories `bin`, `boards` and `software` where simply copied from GRLIB and contain scripts, templates and small programs used by GRLIB. The directory `doc` constains the documentation from GRLIB (may be updated with ReonV specific documentation on future). Directory `designs` contains all scripts and configuration designs for each specific FPGA board supported by Leon3 (and by ReonV). Directory `lib` constains the source code of the processor and of all peripherals or IP cores provided by GRLIB, the 7-stage integer pipeline changed to RISC-V is at `lib/gaisler/leon3v3/iu3.vhd`. Lastly, `riscv` contains scripts and configuration files to run a test example on ReonV (check [Running an Example](#running) section). 
 
 ---
 ## <a name="install"></a> Installation
 ### <a name="install-reonv"></a> ReonV
-As already explained, ReonV is a modified version of the Leon3 processor, which is part of GRLIB, that means you can clone this repository and follow the detailed instructions provided in the GRLIB User Manual (it can be found at doc/grlib.pdf or [here](http://www.gaisler.com/products/grlib/grlib.pdf)) depending on the tools you want to use for synthesis or simulation or even on which FPGA you are goind to run.
+As already explained, ReonV is a modified version of the Leon3 processor, which is part of GRLIB, that means you can clone this repository and follow the detailed instructions provided in the GRLIB User Manual (it can be found at `doc/grlib.pdf` or [here](http://www.gaisler.com/products/grlib/grlib.pdf)) depending on the tools you want to use for synthesis or simulation or even on which FPGA you are going to run.
 ### <a name="rv-toolchain"></a> RISC-V Toolchain
-Needed to compile a program targeting RISC-V architecture, its repository can be found [here](https://github.com/riscv/riscv-gnu-toolchain)
+It is needed to compile a program targeting RISC-V architecture, its repository can be found [here](https://github.com/riscv/riscv-gnu-toolchain). Follow the instructions provided there and make sure to compile it for RV32I only! You can make this by replacing the line `./configure --prefix=/the/path/you/chose` explained on their README to `./configure --with-arch=rv32i --with-abi=ilp32 --prefix=/the/path/you/chose`.
 ### <a name="install-grmon"></a> GRMON2
 GRMON2 is the Leon3 debugging tool provided by [Cobham Gaisler AB](http://www.gaisler.com/). It communicates with the Debugging Unit of the processor and allows to easily execute programs and debug the processor. GRMON has evaluation and professional versions, you can find the download links and its manual [here](http://www.gaisler.com/index.php/downloads/debug-tools).
 

riscv/README.md

@@ -6,17 +6,13 @@ changing a few commands to the ones your board requires.
 ---
 ## Overview
 * ReonV currentily implements RV32I without privilegied instructions, so it is important to use a compiler to this ISA (follow instructions on the main README). 
-* We will use GRMON2 to load, run and debug the program, since the processor DSU was not changed and it communicates with GRMON. However, GRMON2 was not designed for RISC-V and we have to change the assembly and binary to workaround this problem (more information on issue [GRMON2 and RISCV](https://github.com/lcbcFoo/ReonV/issues/5)
+* We will use GRMON2 to load, run and debug the program, since the processor DSU was not changed and it communicates with GRMON. However, GRMON2 was not designed for RISC-V and we have to take some workarounds to run a RISC-V program using it (more information on issue [GRMON2 and RISCV](https://github.com/lcbcFoo/ReonV/issues/5)
 * The scrips for running on nexys4ddr are at `designs/leon3-digilent-nexys4ddr`. If you are running on other board, you must use its own design directory.
 
 ## Compiling the program
-We have files `main.c`, `main.s`, `main.S` and `main.bin`. `main.c` contains our simple example, `main.s` was generated after running `make main.s`, `main.S` is the modified assembly we are going to assemble and finally `main.bin` is the binary generated after assembling `main.S` and extracting .text section, it is the binary we are going to run. The process of compilation is:
+Currently, we have a simple `crt0.S` to initialize stack and other registers. Also, we have some minimal posix functions needed for benchmarks implemented on `posix.c`. These file are linked to the main.c program by the linker script, allowing us to use some commom functions from glibc. However, we do not have complete support for glibc at this moment. The linker script also sets the beginning of `.text` to position 0x40001000 (a workaround needed to run via GRMON2). To compile a program `main.c` on the `riscv` directory run:   
 ```
-make main.s
-# Modify main.s to main.S. We need to set stack point, change `call` commands to `jal`, 
-# since after we remove .text section the calculation for `call` will be wrong. 
-# Put an instruction EBREAK to stop the program.
-make main.bin   # This will assemble main.S and extract .text section 
+make main.out
 ```
 
 ---
@@ -43,9 +39,10 @@ grmon -digilent -u
 ```
 
 ## Running the program
-GRMON2 has many features, but some as still restricted because of our RISC-V ISA. To load and our program use:
+GRMON2 has many features, but some are still restricted because of our RISC-V ISA. To load and our program use:
 ```
-bload ../../riscv/main.bin 0x40000000   # Load on memory position 0x40000000
+bload ../../riscv/main.out 0x40000000   # Load on memory position 0x40000000
+ep 0x40001000                           # Set entry point to position 0x40001000
 run
 ```
-You can `reset` the processor, see the registers with `reg`, set a breakpoint with `bp <address>`, run step by step with `step` and disassemble memory with `disassemble <memory address>`
+You can `reset` the processor, see the registers with `reg`, set a breakpoint with `bp <address>`, run step by step with `step`, disassemble memory with `disassemble <memory address>` and a lot of others commands described on GRMON2´s [manual](http://www.gaisler.com/doc/grmon2.pdf).