mirror of
https://github.com/lcbcFoo/ReonV.git
synced 2025-04-18 18:44:43 -04:00
Special registers implemented, started implementing CRS instructions
This commit is contained in:
lcbcFoo
parent
2ee9d1fe05
commit
1b8a35623f
6 changed files with 135 additions and 123 deletions
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@ -1357,7 +1357,7 @@ architecture rtl of iu3 is
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s.paw := '0';
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s.awp := (others => '0');
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s.stwin := (others => '0');
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s.cwpmax := CWPMAX;
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s.cwpmax := "000";
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s.ducnt := '1';
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return s;
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end function special_register_res;
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@ -1466,21 +1466,21 @@ architecture rtl of iu3 is
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begin
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vcwp := cwp;
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ra := (others => '0'); ra(4 downto 0) := reg;
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if RFPART then
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if ra(4)='0' and cwp=CWPMIN then
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ra(4):='1';
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vcwp := std_logic_vector(unsigned(de_cwpmax) + unsigned(stwin));
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else
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vcwp := std_logic_vector(unsigned(cwp) + unsigned(stwin));
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end if;
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end if;
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if reg(4 downto 3) = "00" then ra(RFBITS -1 downto 4) := globals;
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else
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ra(NWINLOG2+3 downto 4) := vcwp + ra(4);
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if ra(RFBITS-1 downto 4) = globals then
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ra(RFBITS-1 downto 4) := (others => '0');
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end if;
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end if;
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-- if RFPART then
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-- if ra(4)='0' and cwp=CWPMIN then
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-- ra(4):='1';
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-- vcwp := std_logic_vector(unsigned(de_cwpmax) + unsigned(stwin));
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-- else
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-- vcwp := std_logic_vector(unsigned(cwp) + unsigned(stwin));
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-- end if;
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-- end if;
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-- if reg(4 downto 3) = "00" then ra(RFBITS -1 downto 4) := globals;
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-- else
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-- ra(NWINLOG2+3 downto 4) := vcwp + ra(4);
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-- if ra(RFBITS-1 downto 4) = globals then
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-- ra(RFBITS-1 downto 4) := (others => '0');
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-- end if;
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-- end if;
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rao := ra;
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end;
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@ -1671,8 +1671,10 @@ begin
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when R_CONTROL =>
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if(inst(14 downto 12) = R_F3_ECALL) and (inst(20) = '1') then --ebreak
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illegal_inst := '1';
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end if;
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elsif(inst(14 downto 12) = R_F3_ECALL) then -- ecall
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privileged_inst := '1';
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end if;
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when others =>
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illegal_inst := '1';
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end case;
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@ -1708,41 +1710,48 @@ end;
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procedure cwp_gen(r, v : registers; annul, wcwp : std_ulogic; ncwp : cwptype;
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cwp : out cwptype; awp: out cwptype; aw,paw: out std_ulogic;
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stwin,de_cwpmax: out cwptype) is
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begin
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if (r.x.rstate = trap) or
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(r.x.rstate = dsu2)
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or (rstn = '0') then cwp := v.w.s.cwp;
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elsif (wcwp = '1') and (annul = '0') and ((not AWPEN) or r.d.aw='0') then cwp := ncwp;
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elsif r.m.wcwp = '1' then cwp := r.m.result(NWINLOG2-1 downto 0);
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else cwp := r.d.cwp; end if;
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begin
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-- if (r.x.rstate = trap) or
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-- (r.x.rstate = dsu2)
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-- or (rstn = '0') then cwp := v.w.s.cwp;
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-- elsif (wcwp = '1') and (annul = '0') and ((not AWPEN) or r.d.aw='0') then cwp := ncwp;
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-- elsif r.m.wcwp = '1' then cwp := r.m.result(NWINLOG2-1 downto 0);
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-- else cwp := r.d.cwp; end if;
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--
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-- if AWPEN and ((r.x.rstate = trap) or
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-- (r.x.rstate = dsu2)
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-- or (rstn = '0')) then awp := v.w.s.awp;
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-- elsif AWPEN and r.d.aw='1' and (wcwp = '1') and (annul = '0') then awp := ncwp;
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-- elsif AWPEN and r.m.wawp = '1' then awp := r.m.result(NWINLOG2-1 downto 0);
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-- elsif AWPEN and (r.d.aw='0' and r.d.paw='0') then awp := r.d.cwp;
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-- else awp := r.d.awp; end if;
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--
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-- if AWPEN and (
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-- (r.x.rstate = trap) or
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-- (r.x.rstate = dsu2)
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-- or (rstn = '0') ) then aw := v.w.s.aw; paw := v.w.s.paw;
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-- elsif AWPEN and (v.a.ctrl.rett='1') then
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-- aw := r.d.paw; paw := r.d.paw;
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-- elsif AWPEN and r.m.wcwp='1' then aw:=r.m.result(15); paw:=r.m.result(14);
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-- else aw:=r.d.aw; paw:=r.d.paw; end if;
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--
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-- if RFPART and (
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-- (r.x.rstate = trap) or
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-- (r.x.rstate = dsu2)
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-- or (rstn = '0') ) then
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-- stwin := v.w.s.stwin; de_cwpmax:=v.w.s.cwpmax;
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-- elsif RFPART and r.m.wawp='1' and r.m.result(15+NWINLOG2 downto 16)/=CWPMIN then
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-- stwin:=r.m.result(20+NWINLOG2 downto 21); de_cwpmax:=r.m.result(15+NWINLOG2 downto 16);
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-- else
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-- stwin := r.d.stwin; de_cwpmax:=r.d.cwpmax;
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-- end if;
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if AWPEN and ((r.x.rstate = trap) or
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(r.x.rstate = dsu2)
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or (rstn = '0')) then awp := v.w.s.awp;
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elsif AWPEN and r.d.aw='1' and (wcwp = '1') and (annul = '0') then awp := ncwp;
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elsif AWPEN and r.m.wawp = '1' then awp := r.m.result(NWINLOG2-1 downto 0);
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elsif AWPEN and (r.d.aw='0' and r.d.paw='0') then awp := r.d.cwp;
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else awp := r.d.awp; end if;
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if AWPEN and (
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(r.x.rstate = trap) or
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(r.x.rstate = dsu2)
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or (rstn = '0') ) then aw := v.w.s.aw; paw := v.w.s.paw;
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elsif AWPEN and (v.a.ctrl.rett='1') then
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aw := r.d.paw; paw := r.d.paw;
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elsif AWPEN and r.m.wcwp='1' then aw:=r.m.result(15); paw:=r.m.result(14);
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else aw:=r.d.aw; paw:=r.d.paw; end if;
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if RFPART and (
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(r.x.rstate = trap) or
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(r.x.rstate = dsu2)
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or (rstn = '0') ) then
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stwin := v.w.s.stwin; de_cwpmax:=v.w.s.cwpmax;
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elsif RFPART and r.m.wawp='1' and r.m.result(15+NWINLOG2 downto 16)/=CWPMIN then
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stwin:=r.m.result(20+NWINLOG2 downto 21); de_cwpmax:=r.m.result(15+NWINLOG2 downto 16);
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else
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stwin := r.d.stwin; de_cwpmax:=r.d.cwpmax;
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end if;
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cwp := "000";
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aw := '0';
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paw := '0';
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awp := "000";
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stwin := "000";
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de_cwpmax := "000";
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end;
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-- generate wcwp in ex stage
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@ -1751,21 +1760,21 @@ procedure cwp_ex(r : in registers; wcwp : out std_ulogic; wawp : out std_ulogic
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variable vwcwp, vwawp: std_ulogic;
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begin
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vwcwp := '0'; vwawp := '0';
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if (r.e.ctrl.inst(31 downto 30) = FMT3) and
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(r.e.ctrl.inst(24 downto 19) = WRPSR) and
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(pwrpsr=0 or r.e.ctrl.inst(29 downto 25)="00000")
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then vwcwp := not r.e.ctrl.annul; else vwcwp := '0'; end if;
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if AWPEN and
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(r.e.ctrl.inst(31 downto 30) = FMT3) and
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(r.e.ctrl.inst(24 downto 19) = WRY) and
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(r.e.ctrl.inst(29 downto 25) = "10100")
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then
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vwawp := not r.e.ctrl.annul;
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vwcwp := vwcwp or (r.e.op1(5) and not r.e.ctrl.annul);
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else vwawp := '0';
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end if;
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wcwp := vwcwp;
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wawp := vwawp;
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-- if (r.e.ctrl.inst(31 downto 30) = FMT3) and
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-- (r.e.ctrl.inst(24 downto 19) = WRPSR) and
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-- (pwrpsr=0 or r.e.ctrl.inst(29 downto 25)="00000")
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-- then vwcwp := not r.e.ctrl.annul; else vwcwp := '0'; end if;
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-- if AWPEN and
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-- (r.e.ctrl.inst(31 downto 30) = FMT3) and
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-- (r.e.ctrl.inst(24 downto 19) = WRY) and
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-- (r.e.ctrl.inst(29 downto 25) = "10100")
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-- then
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-- vwawp := not r.e.ctrl.annul;
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-- vwcwp := vwcwp or (r.e.op1(5) and not r.e.ctrl.annul);
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-- else vwawp := '0';
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-- end if;
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-- wcwp := vwcwp;
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-- wawp := vwawp;
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end;
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-- generate next cwp & window under- and overflow traps
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@ -1780,22 +1789,22 @@ begin
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op := inst(31 downto 30); op3 := inst(24 downto 19);
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wovf_exc := '0'; wunf_exc := '0'; wim := (others => '0');
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wim(NWIN-1 downto 0) := xc_wim; wcwp := '0';
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ncwp := rcwp;
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if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
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wcwp := '1';
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if (op3 = SAVE) then
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if RFPART and (rcwp=CWPMIN) then ncwp := r.w.s.cwpmax;
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elsif (not CWPOPT) and (rcwp = CWPMIN) then ncwp := CWPMAX;
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else ncwp := rcwp - 1 ; end if;
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else
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if RFPART and (rcwp = r.w.s.cwpmax) then ncwp := CWPMIN;
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elsif (not CWPOPT) and (rcwp = CWPMAX) then ncwp := CWPMIN;
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else ncwp := rcwp + 1; end if;
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end if;
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if wim(conv_integer(ncwp)) = '1' then
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if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
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end if;
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end if;
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ncwp := "000";
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-- if (op = FMT3) and ((op3 = RETT) or (op3 = RESTORE) or (op3 = SAVE)) then
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-- wcwp := '1';
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-- if (op3 = SAVE) then
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-- if RFPART and (rcwp=CWPMIN) then ncwp := r.w.s.cwpmax;
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-- elsif (not CWPOPT) and (rcwp = CWPMIN) then ncwp := CWPMAX;
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-- else ncwp := rcwp - 1 ; end if;
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-- else
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-- if RFPART and (rcwp = r.w.s.cwpmax) then ncwp := CWPMIN;
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-- elsif (not CWPOPT) and (rcwp = CWPMAX) then ncwp := CWPMIN;
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-- else ncwp := rcwp + 1; end if;
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-- end if;
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-- if wim(conv_integer(ncwp)) = '1' then
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-- if op3 = SAVE then wovf_exc := '1'; else wunf_exc := '1'; end if;
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-- end if;
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-- end if;
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de_cwp := ncwp;
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end;
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@ -1936,7 +1945,7 @@ end;
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de_fins_holdx := BPRED and fins and (r.a.bp or r.e.bp); -- skip BP on FPU inst in branch target address
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de_fins_hold := de_fins_holdx;
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ldlock := ldlock or y_hold or fpc_lock or (BPRED and r.a.bp and de_wcwp) or de_fins_holdx;
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ldlock := ldlock or y_hold or fpc_lock or (BPRED and r.a.bp) or de_fins_holdx;
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if ((icc_check_bp and BPRED) = '1') and ((r.a.nobp or mul_hold) = '0') then
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bp := bicc_hold_bp;
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else ldlock := ldlock or bicc_hold or bicc_hold_bp; end if;
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@ -3246,12 +3255,13 @@ begin
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xc_vectt := '1' & r.x.result(6 downto 0);
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else xc_vectt := "00" & r.x.ctrl.tt; end if;
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if r.w.s.svt = '0' then
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xc_trap_address(31 downto 2) := r.w.s.tba & xc_vectt & "00";
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else
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xc_trap_address(31 downto 2) := r.w.s.tba & "00000000" & "00";
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end if;
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xc_trap_address(2 downto PCLOW) := (others => '0');
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-- if r.w.s.svt = '0' then
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-- xc_trap_address(31 downto 2) := r.w.s.tba & xc_vectt & "00";
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-- else
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-- --xc_trap_address(31 downto 2) := r.w.s.tba & "00000000" & "00";
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-- end if;
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xc_trap_address := r.w.s.evec(31 downto 2);
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xc_wreg := '0'; v.x.annul_all := '0';
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if (not r.x.ctrl.annul and r.x.ctrl.ld) = '1' then
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@ -3273,13 +3283,13 @@ begin
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end if;
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xc_trapcwp := r.w.s.cwp;
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if RFPART then
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if r.w.s.cwp=CWPMIN then
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xc_trapcwp := r.w.twcwp;
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else
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xc_trapcwp := std_logic_vector(unsigned(r.w.s.stwin) + unsigned(r.w.s.cwp));
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end if;
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end if;
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-- if RFPART then
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-- if r.w.s.cwp=CWPMIN then
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-- xc_trapcwp := r.w.twcwp;
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-- else
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-- xc_trapcwp := std_logic_vector(unsigned(r.w.s.stwin) + unsigned(r.w.s.cwp));
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-- end if;
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-- end if;
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if DBGUNIT
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@ -3332,13 +3342,14 @@ begin
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xc_waddr(NWINLOG2 + 3 downto 0) := xc_trapcwp & "0010";
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if r.w.s.et = '1' then
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v.w.s.et := '0'; v.x.rstate := run;
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if RFPART and (r.w.s.cwp = CWPMIN) then v.w.s.cwp := r.w.s.cwpmax;
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elsif (not CWPOPT) and (r.w.s.cwp = CWPMIN) then v.w.s.cwp := CWPMAX;
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else v.w.s.cwp := r.w.s.cwp - 1 ; end if;
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if AWPEN then
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v.w.s.aw := '0';
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v.w.s.paw := r.w.s.aw;
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end if;
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-- change cwp
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-- if RFPART and (r.w.s.cwp = CWPMIN) then v.w.s.cwp := r.w.s.cwpmax;
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-- elsif (not CWPOPT) and (r.w.s.cwp = CWPMIN) then v.w.s.cwp := CWPMAX;
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-- else v.w.s.cwp := r.w.s.cwp - 1 ; end if;
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-- if AWPEN then
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-- v.w.s.aw := '0';
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-- v.w.s.paw := r.w.s.aw;
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-- end if;
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else
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xc_inull := '1';
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v.x.rstate := dsu1; xc_wreg := '0'; vp.error := '1';
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@ -3429,10 +3440,10 @@ begin
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if (r.x.rstate = dsu2) then v.w.except := '0'; end if;
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v.w.wa := xc_waddr(RFBITS-1 downto 0); v.w.wreg := xc_wreg and holdn;
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if RFPART then
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v.w.twcwp := std_logic_vector(unsigned(v.w.s.stwin) + unsigned(v.w.s.cwpmax) + 1);
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if (not CWPOPT) and v.w.twcwp=CWPGLB then v.w.twcwp:=CWPMIN; end if;
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end if;
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-- if RFPART then
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-- v.w.twcwp := std_logic_vector(unsigned(v.w.s.stwin) + unsigned(v.w.s.cwpmax) + 1);
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-- if (not CWPOPT) and v.w.twcwp=CWPGLB then v.w.twcwp:=CWPMIN; end if;
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-- end if;
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rfi.wdata <= xc_result; rfi.waddr <= xc_waddr;
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@ -3453,14 +3464,14 @@ begin
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v.w.except := RRES.w.except; v.w.s.et := RRES.w.s.et;
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v.w.s.svt := RRES.w.s.svt; v.w.s.dwt := RRES.w.s.dwt;
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v.w.s.ef := RRES.w.s.ef;
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if RFPART then
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v.w.s.stwin := RRES.w.s.stwin;
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v.w.s.cwpmax := RRES.w.s.cwpmax;
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end if;
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if need_extra_sync_reset(fabtech) /= 0 then
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v.w.s.cwp := RRES.w.s.cwp;
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v.w.s.icc := RRES.w.s.icc;
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end if;
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-- if RFPART then
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-- v.w.s.stwin := RRES.w.s.stwin;
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-- v.w.s.cwpmax := RRES.w.s.cwpmax;
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-- end if;
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-- if need_extra_sync_reset(fabtech) /= 0 then
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-- v.w.s.cwp := RRES.w.s.cwp;
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-- v.w.s.icc := RRES.w.s.icc;
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-- end if;
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v.w.s.dbp := RRES.w.s.dbp;
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v.w.s.dbprepl := RRES.w.s.dbprepl;
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v.w.s.rexdis := RRES.w.s.rexdis;
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@ -3610,15 +3621,10 @@ begin
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dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load, v.m.casa);
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-- RV32I change
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-- if(r.e.ctrl.inst(6 downto 0) = R_BRANCH) then -- BRANCH
|
||||
--ex_jump_address := branch_address(r.e.ctrl.inst, r.e.ctrl.pc(31 downto PCLOW), de_rexbaddr1, r.d.rexen);
|
||||
-- ex_jump_address := x"4000004" & "00";
|
||||
if(r.e.alusel = EXE_RES_ADD) then -- JALR
|
||||
ex_jump_address := ex_add_res(32 downto PCLOW+1);
|
||||
--ex_jump_address := x"4000003" & "00";
|
||||
else -- JAL
|
||||
ex_jump_address := ex_add_res(32 downto PCLOW+1) + r.e.ctrl.pc(31 downto PCLOW);
|
||||
--ex_jump_address := x"4000004" & "00";
|
||||
end if;
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@ LD_SCRIPT=ld_script
|
|||
#
|
||||
#####################################################################
|
||||
# Compiled binary linked with reonv_crt0
|
||||
%.out : %.c
|
||||
%.out : %.c reonv_crt0.o
|
||||
${CROSS}${CC} -static -T${LD_SCRIPT} $< -o $@
|
||||
|
||||
# Targets for .S.
|
||||
|
|
|
|||
BIN
riscv/main.bin
BIN
riscv/main.bin
Binary file not shown.
|
|
@ -4,6 +4,12 @@
|
|||
|
||||
main:
|
||||
li x4,0x40000100
|
||||
csrr x4,3
|
||||
csrw 3,x5
|
||||
csrrw x0,3,x4
|
||||
csrrs x5,3,x0
|
||||
ecall
|
||||
li x30,0x98765
|
||||
ebreak
|
||||
|
||||
.org 0x100
|
||||
li x31,0x12345
|
||||
ebreak
|
||||
|
|
|
|||
Binary file not shown.
Loading…
Add table
Reference in a new issue