Added running README

README.md

@@ -37,4 +37,4 @@ GRMON2 is the Leon3 debugging tool provided by [Cobham Gaisler AB](http://www.ga
 
 ---
 ## <a name="running"></a> Running an Example
-
+Follow instructions of the README on `riscv` directory.

riscv/README.md

@@ -0,0 +1,51 @@
+unning an example on nexys4 ddr board
+
+This is an example of how you can run an simple program on ReonV. We will use Nexys4ddr, however to use another board you will follow similar steps, 
+changing a few commands to the ones your board requires.
+
+---
+## Overview
+* ReonV currentily implements RV32I without privilegied instructions, so it is important to use a compiler to this ISA (follow instructions on the main README). 
+* We will use GRMON2 to load, run and debug the program, since the processor DSU was not changed and it communicates with GRMON. However, GRMON2 was not designed for RISC-V and we have to change the assembly and binary to workaround this problem (more information on issue [GRMON2 and RISCV](https://github.com/lcbcFoo/ReonV/issues/5)
+* The scrips for running on nexys4ddr is at `designs/leon3-digilent-nexys4ddr`. If you are running on other board, you must use its own design directory.
+
+## Compiling the program
+We have files `main.c`, `main.s`, `main.S` and `main.bin`. `main.c` contains our simple example, `main.s` was generated after running `make main.s`, `main.S` is the modified assembly we are going to assemble and finally `main.bin` is the binary generated after assembling `main.S` and extracting .text section, it is the binary we are going to run. The process of compilation is:
+```
+make main.s
+# Modify main.s to main.S. We need to set stack point, change `call` commands to `jal`, 
+# since after we remove .text section the calculation for `call` will be wrong. 
+# Put an instruction EBREAK to stop the program.
+make main.bin   # This will assemble main.S and extract .text section 
+```
+
+---
+## Synthetizing and loading design to FPGA
+To synthetize ReonV you must change to your board design directory, in this example it is `designs/leon3-digilent-nexys4ddr`. There is a README in each design directory, follow the instructions there to synthetize and load the design to FPGA. In this example, they are:
+```
+make sim
+make vivado
+make vivado-prog-fpga  # with the FPGA connected to the computer 
+```
+
+---
+## Using GRMON2
+You can follow the instructions of how to communicate with the FPGA using GRMON2 on its [manual](http://www.gaisler.com/doc/grmon2.pdf). On this example, we need to run:
+```
+grmon -digilent -u
+# On GRMON2, we have to run this command as written on nexys4ddr readme
+ddr2delay scan
+# Close GRMON2
+q
+# Reopen GRMON2
+grmon -digilent -u
+# Now we are ready to run the example
+```
+
+## Running the program
+GRMON2 has many features, but some as still restricted because of our RISC-V ISA. To load and our program use:
+```
+bload ../../riscv/main.bin 0x40000000   # Load on memory position 0x40000000
+run
+```
+You can `reset` the processor, see the registers with `reg`, set a breakpoint with `bp <address>`, run step by step with `step` and disassemble memory with `disassemble <memory address>`