mirror of
https://github.com/lcbcFoo/ReonV.git
synced 2025-04-23 13:07:08 -04:00
Cleaning some unused signals from original ISA
This commit is contained in:
lcbcFoo
parent
34bad13737
commit
4380257d84
1 changed files with 25 additions and 651 deletions
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@ -1503,17 +1503,6 @@ architecture rtl of iu3 is
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when others => null;
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end case;
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end if;
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-- n := icc(3); z := icc(2); v := icc(1); c := icc(0);
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-- case inst(27 downto 25) is
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-- when "000" => branch := inst(28) xor '0'; -- bn, ba
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-- when "001" => branch := inst(28) xor z; -- be, bne
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-- when "010" => branch := inst(28) xor (z or (n xor v)); -- ble, bg
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-- when "011" => branch := inst(28) xor (n xor v); -- bl, bge
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-- when "100" => branch := inst(28) xor (c or z); -- bleu, bgu
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-- when "101" => branch := inst(28) xor c; -- bcs, bcc
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-- when "110" => branch := inst(28) xor n; -- bneg, bpos
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-- when others => branch := inst(28) xor v; -- bvs, bvc
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-- end case;
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return(branch);
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end;
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@ -1632,6 +1621,8 @@ variable wph : std_ulogic;
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begin
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inst := r.a.ctrl.inst; trap := trapin; tt := ttin;
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-- Exceptions and traps detection and handling are not completely implemented
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if r.a.ctrl.annul = '0' then
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case inst(6 downto 0) is
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when R_LUI | R_AUIPC | R_JAL | R_JALR | R_BRANCH | R_LD | R_ST | R_IMM
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@ -1641,97 +1632,6 @@ begin
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illegal_inst := '1';
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end case;
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-- if(inst(31 downto 0) = "00000000000100000000000001110011")then
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-- illegal_inst := '1';
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-- elsif(inst(31 downto 0) = "00000000000000000000000001110011")then
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-- illegal_inst := '1';
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-- else
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-- illegal_inst := '0';
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-- end if;
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-- op := inst(31 downto 30); op2 := inst(24 downto 22);
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-- op3 := inst(24 downto 19); rd := inst(29 downto 25);
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-- illegal_inst := '0'; privileged_inst := '0'; cp_disabled := '0';
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-- fp_disabled := '0'; fpop := '0';
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-- case op is
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-- when CALL => null;
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-- when FMT2 =>
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-- case op2 is
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-- when SETHI | BICC => null;
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-- when FBFCC =>
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-- if FPEN then fp_disabled := not r.w.s.ef; else fp_disabled := '1'; end if;
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-- when CBCCC =>
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-- if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
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-- when others => illegal_inst := '1';
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-- end case;
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-- when FMT3 =>
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-- case op3 is
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-- when IAND | ANDCC | ANDN | ANDNCC | IOR | ORCC | ORN | ORNCC | IXOR |
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-- XORCC | IXNOR | XNORCC | ISLL | ISRL | ISRA | MULSCC | IADD | ADDX |
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-- ADDCC | ADDXCC | ISUB | SUBX | SUBCC | SUBXCC | FLUSH | JMPL | TICC |
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-- SAVE | RESTORE | RDY => null;
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-- when TADDCC | TADDCCTV | TSUBCC | TSUBCCTV =>
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-- if notag = 1 then illegal_inst := '1'; end if;
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-- when UMAC | SMAC =>
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-- if not MACEN then illegal_inst := '1'; end if;
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-- when UMUL | SMUL | UMULCC | SMULCC =>
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-- if not MULEN then illegal_inst := '1'; end if;
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-- when UDIV | SDIV | UDIVCC | SDIVCC =>
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-- if not DIVEN then illegal_inst := '1'; end if;
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-- when RETT => illegal_inst := r.a.et; privileged_inst := not r.a.su;
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-- when RDPSR | RDTBR | RDWIM => privileged_inst := not r.a.su;
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-- when WRY =>
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-- if rd(4) = '1' and rd(3 downto 0) /= "0010" then -- %ASR16-17, %ASR19-31
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-- privileged_inst := not r.a.su;
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-- end if;
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-- when WRPSR =>
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-- privileged_inst := not r.a.su;
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-- when WRWIM | WRTBR => privileged_inst := not r.a.su;
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-- when FPOP1 | FPOP2 =>
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-- if FPEN then fp_disabled := not r.w.s.ef; fpop := '1';
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-- else fp_disabled := '1'; fpop := '0'; end if;
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-- when CPOP1 | CPOP2 =>
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-- if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
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-- when others => illegal_inst := '1';
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-- end case;
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-- when others => -- LDST
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-- case op3 is
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-- when LDD | ISTD => illegal_inst := rd(0); -- trap if odd destination register
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-- when LD | LDUB | LDSTUB | LDUH | LDSB | LDSH | ST | STB | STH | SWAP =>
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-- null;
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-- when LDDA | STDA =>
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-- illegal_inst := inst(13) or rd(0);
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-- if (npasi = 0) or (inst(12) = '0') then
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-- privileged_inst := not r.a.su;
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-- end if;
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-- when LDA | LDUBA| LDSTUBA | LDUHA | LDSBA | LDSHA | STA | STBA | STHA |
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-- SWAPA =>
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-- illegal_inst := inst(13);
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-- if (npasi = 0) or (inst(12) = '0') then
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-- privileged_inst := not r.a.su;
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-- end if;
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-- when CASA =>
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-- if CASAEN then
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-- illegal_inst := inst(13);
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-- if (inst(12 downto 5) /= X"0A") then privileged_inst := not r.a.su; end if;
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-- else illegal_inst := '1'; end if;
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-- when LDDF | STDF | LDF | LDFSR | STF | STFSR =>
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-- if FPEN then fp_disabled := not r.w.s.ef;
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-- else fp_disabled := '1'; end if;
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-- when STDFQ =>
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-- privileged_inst := not r.a.su;
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-- if (not FPEN) or (r.w.s.ef = '0') then fp_disabled := '1'; end if;
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-- when STDCQ =>
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-- privileged_inst := not r.a.su;
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-- if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
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-- when LDC | LDCSR | LDDC | STC | STCSR | STDC =>
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-- if (not CPEN) or (r.w.s.ec = '0') then cp_disabled := '1'; end if;
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-- when others => illegal_inst := '1';
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-- end case;
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-- end case;
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wph := wphit(r, wpr, dbgi, dsur, pccomp);
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trap := '1';
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@ -1756,39 +1656,6 @@ begin
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if(inst(6 downto 0) = R_BRANCH) then
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wicc := '1';
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end if;
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-- if inst(31 downto 30) = FMT3 then
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-- case inst(24 downto 19) is
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-- when SUBCC | TSUBCC | TSUBCCTV | ADDCC | ANDCC | ORCC | XORCC | ANDNCC |
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-- ORNCC | XNORCC | TADDCC | TADDCCTV | ADDXCC | SUBXCC | WRPSR =>
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-- wicc := '1';
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-- if (pwrpsr /= 0) and inst(24 downto 19)=WRPSR and inst(29 downto 25)/="00000" then
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-- wicc := '0';
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-- end if;
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-- when WRY =>
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-- if REX=0 then
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-- if r.d.inst(conv_integer(r.d.set))(29 downto 25) = "00000" then wy := '1'; end if;
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-- else
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-- if inst(29 downto 25) = "00000" then wy := '1'; end if;
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-- end if;
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-- when MULSCC =>
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-- wicc := '1'; wy := '1';
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-- when UMAC | SMAC =>
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-- if MACEN then wy := '1'; end if;
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-- when UMULCC | SMULCC =>
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-- if MULEN and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
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-- wicc := '1'; wy := '1';
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-- end if;
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-- when UMUL | SMUL =>
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-- if MULEN and (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
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-- wy := '1';
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-- end if;
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-- when UDIVCC | SDIVCC =>
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-- if DIVEN and (divo.nready = '1') and (r.d.cnt /= "00") then
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-- wicc := '1';
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-- end if;
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-- when others =>
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-- end case;
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-- end if;
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end;
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-- select cwp
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@ -1901,20 +1768,6 @@ procedure rs1_gen(r : registers; inst : word; rs1 : out std_logic_vector(4 down
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if(inst(6 downto 0) = R_ST and r.d.cnt = "01")then
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rs1 := inst(24 downto 20);
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end if;
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-- variable op : std_logic_vector(1 downto 0);
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-- variable op3 : std_logic_vector(5 downto 0);
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-- begin
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-- op := inst(31 downto 30); op3 := inst(24 downto 19);
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-- rs1 := inst(18 downto 14); rs1mod := '0';
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-- if (op = LDST) then
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-- if ((r.d.cnt = "01") and ((op3(2) and not op3(3)) = '1')) or
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-- ((r.d.cnt = "10") and (not (CASAEN and LDDEL=2 and op3(5 downto 3)="111"))) or
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-- ((r.d.cnt = "11") and ( (CASAEN and LDDEL=2)))
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-- then rs1mod := '1'; rs1 := inst(29 downto 25); end if;
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-- if ((r.d.cnt = "10") and (op3(3 downto 0) = "0111")) then
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-- rs1(0) := '1';
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-- end if;
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-- end if;
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end;
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-- load/icc interlock detection
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@ -1930,7 +1783,6 @@ end;
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variable miss : std_logic;
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begin
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miss := (not r.e.ctrl.annul) and r.e.bp and not branch_true(icc, r.e.ctrl.inst);
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--ra_bpannul := miss and r.e.ctrl.inst(29);
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ra_bpannul := miss;
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ex_bpmiss := miss;
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end;
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@ -1940,7 +1792,6 @@ end;
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variable miss : std_logic;
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begin
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miss := ((not r.a.ctrl.annul) and r.a.bp and icc_valid(r) and not branch_true(r.m.icc, r.a.ctrl.inst));
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--de_bpannul := miss and r.a.ctrl.inst(29;
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de_bpannul := miss;
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ra_bpmiss := miss;
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end;
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@ -1991,12 +1842,10 @@ end;
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ldcheck1 := '1'; ldchkra := '0';
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case r.d.cnt is
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when "00" =>
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--if (lddel = 2) and (op3(2) = '1') and (op3(5) = '0') then ldcheck3 := '1'; end if;
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if (op(5) = '1') then ldcheck3 := '1'; end if; -- store
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ldchkra := '1';
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when "01" =>
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ldchkra := '1';
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--if (op 3(5) and op3(2) and not op3(3)) = '1' then ldcheck1 := '0'; ldcheck2 := '0'; end if; -- STF/STC
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when others => NULL;
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end case;
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when others => null;
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@ -2004,62 +1853,6 @@ end;
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end if;
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--------------------------------------------------------------------------------
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-- if (r.d.annul = '0') and (icbpmiss='0')
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-- then
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-- case op is
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-- when CALL =>
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-- call_hold := '1'; nobp := BPRED;
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-- when FMT2 =>
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-- if (op2 = BICC) and (cond(2 downto 0) /= "000") then
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-- icc_check_bp := '1';
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-- end if;
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-- if (op2 = BICC) then nobp := BPRED; end if;
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-- when FMT3 =>
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-- ldcheck1 := '1'; ldcheck2 := not i;
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-- case op3 is
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-- when TICC =>
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-- if (cond(2 downto 0) /= "000") then icc_check := '1'; end if;
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-- nobp := BPRED;
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-- when RDY =>
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-- ldcheck1 := '0'; ldcheck2 := '0';
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-- if MACPIPE then y_check := '1'; end if;
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-- when RDWIM | RDTBR =>
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-- ldcheck1 := '0'; ldcheck2 := '0';
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-- when RDPSR =>
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-- ldcheck1 := '0'; ldcheck2 := '0'; icc_check := '1';
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-- when SDIV | SDIVCC | UDIV | UDIVCC =>
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-- if DIVEN then y_check := '1'; nobp := op3(4); end if; -- no BP on divcc
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-- when FPOP1 | FPOP2 => ldcheck1:= '0'; ldcheck2 := '0'; fins := BPRED;
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-- when JMPL => call_hold := '1'; nobp := BPRED;
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-- when others =>
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-- end case;
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-- when LDST =>
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-- ldcheck1 := '1'; ldchkra := '0';
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-- case r.d.cnt is
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-- when "00" =>
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-- if (lddel = 2) and (op3(2) = '1') and (op3(5) = '0') then ldcheck3 := '1'; end if;
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-- ldcheck2 := not i; ldchkra := '1';
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-- when "01" =>
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-- ldcheck2 := not i;
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-- if (op3(5) and op3(2) and not op3(3)) = '1' then ldcheck1 := '0'; ldcheck2 := '0'; end if; -- STF/STC
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-- when others => ldchkex := '0';
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-- if CASAEN and (op3(5 downto 3) = "111") then
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-- if lddel=2 then
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-- ldcheck2 := r.d.cnt(0);
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-- else
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-- ldcheck2 := '1';
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-- end if;
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-- elsif (op3(5) = '1') or ((op3(5) & op3(3 downto 1)) = "0110") -- LDST
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-- then ldcheck1 := '0'; ldcheck2 := '0'; end if;
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-- end case;
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-- if op3(5) = '1' then fins := BPRED; end if; -- no BP on FPU/CP LD/ST
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-- when others => null;
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-- end case;
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-- end if;
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if MULEN or DIVEN then
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chkmul := mulinsn;
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mul_hold := (r.a.mulstart and r.a.ctrl.wicc) or (r.m.ctrl.wicc and (r.m.ctrl.cnt(0) or r.m.mul));
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@ -2206,22 +1999,6 @@ end;
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if ((exbpmiss and not r.a.ctrl.annul and not r.d.pv and not hold_pc) = '1') then
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annul_next := '1'; pv := '0';
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end if;
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-- if ((exbpmiss and r.e.ctrl.inst(29) and not r.a.ctrl.annul and not r.d.pv ) = '1')
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-- and (r.d.cnt = "01") then
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-- annul_next := '1'; annul_current := '1'; pv := '0';
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-- end if;
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-- if (exbpmiss and r.e.ctrl.inst(29) and r.a.ctrl.annul and r.d.pv) = '1' then
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-- annul_next := '1'; pv := '0'; inhibit_current := '1';
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-- end if;
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-- if (exbpmiss and r.e.ctrl.inst(29) and BLOCKBPMISS and r.a.bpimiss) = '1' then
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-- annul_next := '1'; pv := '0';
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-- end if;
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-- if (rabpmiss and not r.a.ctrl.inst(29) and not r.d.annul and r.d.pv and not hold_pc) = '1' then
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-- annul_next := '1'; pv := '0';
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-- end if;
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-- if (rabpmiss and r.a.ctrl.inst(29 and not r.d.annul and r.d.pv ) = '1' then
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-- annul_next := '1'; pv := '0'; inhibit_current := '1';
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-- end if;
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if irqlat/=0 and r.d.irqstart='1' and r.d.irqlatmet='0' then
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annul_current := '1';
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@ -2290,56 +2067,6 @@ end;
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write_reg := '0';
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end if;
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wreg := write_reg; rdo := rd; rexen := vrexen;
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----------------------------------------------------------------------------
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-- case op is
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-- when CALL =>
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-- write_reg := '1'; rd := "01111"; -- CALL saves PC in r[15] (%o7)
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-- when FMT2 =>
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-- if (op2 = SETHI) then write_reg := '1'; end if;
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-- when FMT3 =>
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-- case op3 is
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-- when UMUL | SMUL | UMULCC | SMULCC =>
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-- if MULEN then
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-- if (((mulo.nready = '1') and (r.d.cnt /= "00")) or (MULTYPE /= 0)) then
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-- write_reg := '1';
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-- end if;
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-- else write_reg := '1'; end if;
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-- when UDIV | SDIV | UDIVCC | SDIVCC =>
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-- if DIVEN then
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-- if (divo.nready = '1') and (r.d.cnt /= "00") then
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-- write_reg := '1';
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-- end if;
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-- else write_reg := '1'; end if;
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-- when RETT | WRPSR | WRY | WRWIM | WRTBR | TICC | FLUSH => null;
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-- when FPOP1 | FPOP2 => null;
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-- when CPOP1 | CPOP2 => null;
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-- when SAVE | IADD =>
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-- write_reg := '1';
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-- if REX /= 0 and inst(13)='0' and inst(12)='1' then
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-- vrexen := '1';
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-- end if;
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-- when others => write_reg := '1';
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-- end case;
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-- when others => -- LDST
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-- ld := not op3(2);
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-- if (op3(2) = '0') and not ((CPEN or FPEN) and (op3(5) = '1'))
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-- then write_reg := '1'; end if;
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-- case op3 is
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-- when SWAP | SWAPA | LDSTUB | LDSTUBA | CASA =>
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-- if r.d.cnt = "00" then write_reg := '1'; ld := '1'; end if;
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-- when others => null;
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-- end case;
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-- if r.d.cnt = "01" then
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-- case op3 is
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-- when LDD | LDDA | LDDC | LDDF => rd(0) := '1';
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-- when others =>
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-- end case;
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-- end if;
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-- end case;
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--
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-- if (rd = "00000") then write_reg := '0'; end if;
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-- wreg := write_reg; rdo := rd; rexen := vrexen;
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end;
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-- immediate data generation
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@ -2404,24 +2131,6 @@ end;
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imm := false;
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end if;
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return(imm);
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-- if REX=1 and de_rexen='1' then imm:=true; end if;
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-- case inst(31 downto 30) is
|
||||
-- when FMT2 =>
|
||||
-- case inst(24 downto 22) is
|
||||
-- when SETHI => imm := true;
|
||||
-- when others =>
|
||||
-- end case;
|
||||
-- when FMT3 =>
|
||||
-- case inst(24 downto 19) is
|
||||
-- when RDWIM | RDPSR | RDTBR => imm := true;
|
||||
-- when others => if (inst(13) = '1') then imm := true; end if;
|
||||
-- end case;
|
||||
-- when LDST =>
|
||||
-- if (inst(13) = '1') then imm := true; end if;
|
||||
-- when others =>
|
||||
-- end case;
|
||||
-- return(imm);
|
||||
end;
|
||||
|
||||
-- EXE operation
|
||||
|
|
@ -2433,8 +2142,6 @@ end;
|
|||
mulins, divins, mulstep, macins, ldbp2, invop2 : out std_logic
|
||||
) is
|
||||
variable op : std_logic_vector(6 downto 0);
|
||||
--variable op2 : std_logic_vector(2 downto 0);
|
||||
--variable op3 : std_logic_vector(5 downto 0);
|
||||
variable f3 : std_logic_vector(2 downto 0);
|
||||
variable rs1, rs2, rd : std_logic_vector(4 downto 0);
|
||||
variable icc : std_logic_vector(3 downto 0);
|
||||
|
|
@ -2462,9 +2169,8 @@ end;
|
|||
elsif r.x.ctrl.wicc = '1' then icc := r.x.icc;
|
||||
else icc := r.w.s.icc; end if;
|
||||
|
||||
--------------------------------------------------------------------
|
||||
--TODO: finish
|
||||
-- RISCV32I operations
|
||||
|
||||
-- Generate ALU operation
|
||||
case op is
|
||||
when R_AUIPC =>
|
||||
aluop := EXE_AUIPC;
|
||||
|
|
@ -2547,83 +2253,9 @@ end;
|
|||
end case;
|
||||
when others => null;
|
||||
end case;
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
-- case op is
|
||||
-- when CALL =>
|
||||
-- aluop := EXE_LINK;
|
||||
-- when FMT2 =>
|
||||
-- case op2 is
|
||||
-- when SETHI => aluop := EXE_PASS2;
|
||||
-- when others =>
|
||||
-- end case;
|
||||
-- when FMT3 =>
|
||||
-- case op3 is
|
||||
-- when IADD | ADDX | ADDCC | ADDXCC | TADDCC | TADDCCTV | SAVE | RESTORE |
|
||||
-- TICC | JMPL | RETT =>
|
||||
-- alusel := EXE_RES_ADD;
|
||||
-- if REX=1 then aluop := EXE_LINK; end if;
|
||||
-- when ISUB | SUBX | SUBCC | SUBXCC | TSUBCC | TSUBCCTV =>
|
||||
-- alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
|
||||
-- when MULSCC => alusel := EXE_RES_ADD;
|
||||
-- aop1 := (icc(3) xor icc(1)) & iop1(31 downto 1);
|
||||
-- if y0 = '0' then aop2 := (others => '0'); ldbp2 := '0'; end if;
|
||||
-- mulstep := '1';
|
||||
-- when UMUL | UMULCC | SMUL | SMULCC =>
|
||||
-- if MULEN then mulins := '1'; end if;
|
||||
-- when UMAC | SMAC =>
|
||||
-- if MACEN then mulins := '1'; macins := '1'; end if;
|
||||
-- when UDIV | UDIVCC | SDIV | SDIVCC =>
|
||||
-- if DIVEN then
|
||||
-- aluop := EXE_DIV; alusel := EXE_RES_LOGIC; divins := '1';
|
||||
-- end if;
|
||||
-- when IAND | ANDCC => aluop := EXE_AND; alusel := EXE_RES_LOGIC;
|
||||
-- when ANDN | ANDNCC => aluop := EXE_ANDN; alusel := EXE_RES_LOGIC;
|
||||
-- when IOR | ORCC => aluop := EXE_OR; alusel := EXE_RES_LOGIC;
|
||||
-- when ORN | ORNCC => aluop := EXE_ORN; alusel := EXE_RES_LOGIC;
|
||||
-- when IXNOR | XNORCC => aluop := EXE_XNOR; alusel := EXE_RES_LOGIC;
|
||||
-- when XORCC | IXOR | WRPSR | WRWIM | WRTBR | WRY =>
|
||||
-- aluop := EXE_XOR; alusel := EXE_RES_LOGIC;
|
||||
-- when RDPSR | RDTBR | RDWIM => aluop := EXE_SPR;
|
||||
-- when RDY => aluop := EXE_RDY;
|
||||
-- when ISLL => aluop := EXE_SLL; alusel := EXE_RES_SHIFT; shleft := '1';
|
||||
-- shcnt := not iop2(4 downto 0); invop2 := '1';
|
||||
-- when ISRL => aluop := EXE_SRL; alusel := EXE_RES_SHIFT;
|
||||
-- when ISRA => aluop := EXE_SRA; alusel := EXE_RES_SHIFT; sari := iop1(31);
|
||||
-- when FPOP1 | FPOP2 =>
|
||||
-- when others =>
|
||||
-- end case;
|
||||
-- when others => -- LDST
|
||||
-- case r.a.ctrl.cnt is
|
||||
-- when "00" =>
|
||||
-- alusel := EXE_RES_ADD;
|
||||
-- when "01" =>
|
||||
-- case op3 is
|
||||
-- when LDD | LDDA | LDDC => alusel := EXE_RES_ADD;
|
||||
-- when LDDF => alusel := EXE_RES_ADD;
|
||||
-- when SWAP | SWAPA | LDSTUB | LDSTUBA | CASA => alusel := EXE_RES_ADD;
|
||||
-- when STF | STDF =>
|
||||
-- when others =>
|
||||
-- aluop := EXE_PASS1;
|
||||
-- if op3(2) = '1' then
|
||||
-- if op3(1 downto 0) = "01" then aluop := EXE_STB;
|
||||
-- elsif op3(1 downto 0) = "10" then aluop := EXE_STH; end if;
|
||||
-- end if;
|
||||
-- end case;
|
||||
-- when "10" =>
|
||||
-- aluop := EXE_PASS1;
|
||||
-- if op3(2) = '1' then -- ST
|
||||
-- if (op3(3) and not op3(5) and not op3(1))= '1' then aluop := EXE_ONES; end if; -- LDSTUB
|
||||
-- end if;
|
||||
-- if CASAEN and (r.m.casa = '1') and LDDEL=1 then
|
||||
-- alusel := EXE_RES_ADD; aluadd := '0'; aop2 := not iop2; invop2 := '1';
|
||||
-- end if;
|
||||
-- when others =>
|
||||
-- end case;
|
||||
-- end case;
|
||||
end;
|
||||
|
||||
|
||||
function ra_inull_gen(r, v : registers) return std_ulogic is
|
||||
variable de_inull : std_ulogic;
|
||||
begin
|
||||
|
|
@ -2691,37 +2323,18 @@ end;
|
|||
cin := '1';
|
||||
when others => null;
|
||||
end case;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
-- case op is
|
||||
-- when FMT3 =>
|
||||
-- case op3 is
|
||||
-- when ISUB | SUBCC | TSUBCC | TSUBCCTV => cin := '1';
|
||||
-- when ADDX | ADDXCC => cin := ncin;
|
||||
-- when SUBX | SUBXCC => cin := not ncin;
|
||||
-- when others => null;
|
||||
-- end case;
|
||||
-- when LDST =>
|
||||
-- if CASAEN and (r.m.casa = '1') and
|
||||
-- ((r.a.ctrl.cnt = "10" and LDDEL=1) or (r.a.ctrl.cnt = "11" and LDDEL=2)) then
|
||||
-- cin := '1';
|
||||
-- end if;
|
||||
-- when others => null;
|
||||
-- end case;
|
||||
end;
|
||||
|
||||
|
||||
procedure logic_op(r : registers; aluin1, aluin2, mey : word;
|
||||
ymsb : std_ulogic; logicres, y : out word) is
|
||||
variable logicout : word;
|
||||
begin
|
||||
case r.e.aluop is
|
||||
when EXE_AND => logicout := aluin1 and aluin2;
|
||||
--when EXE_ANDN => logicout := aluin1 and not aluin2;
|
||||
when EXE_OR => logicout := aluin1 or aluin2;
|
||||
when EXE_ORN => logicout := aluin1 or not aluin2;
|
||||
when EXE_XOR => logicout := aluin1 xor aluin2;
|
||||
--when EXE_XNOR => logicout := aluin1 xor not aluin2;
|
||||
when EXE_SLT =>
|
||||
if(signed(aluin1) < signed(aluin2)) then
|
||||
logicout(0) := '1';
|
||||
|
|
@ -2736,10 +2349,7 @@ end;
|
|||
logicout(0) := '0';
|
||||
end if;
|
||||
logicout(31 downto 1) := (others => '0');
|
||||
|
||||
--when EXE_DIV =>
|
||||
-- if DIVEN then logicout := aluin2;
|
||||
-- else logicout := (others => '-'); end if;
|
||||
;
|
||||
when others => logicout := (others => '-');
|
||||
end case;
|
||||
if (r.e.ctrl.wy and r.e.mulstep) = '1' then
|
||||
|
|
@ -2773,11 +2383,9 @@ end;
|
|||
wpi := 0;
|
||||
miscout := (others => '0');
|
||||
miscout(31 downto PCLOW) := r.e.ctrl.pc(31 downto PCLOW);
|
||||
if REX/=0 and r.e.ctrl.pc(PCLOW)='1' then
|
||||
miscout(31 downto 2) := miscout(31 downto 2)-1;
|
||||
end if;
|
||||
edata := aluin1;
|
||||
|
||||
-- Dummy endian convertion to store data
|
||||
bpdata(7 downto 0) := aluin1(31 downto 24);
|
||||
bpdata(15 downto 8) := aluin1(23 downto 16);
|
||||
bpdata(23 downto 16) := aluin1(15 downto 8);
|
||||
|
|
@ -2799,56 +2407,10 @@ end;
|
|||
edata := miscout;
|
||||
when EXE_PASS1 => miscout := bpdata; edata := miscout;
|
||||
when EXE_PASS2 => miscout := aluin2;
|
||||
-- when EXE_ONES => miscout := (others => '1');
|
||||
-- edata := miscout;
|
||||
|
||||
when EXE_AUIPC =>
|
||||
miscout := aluin2 + (r.e.ctrl.pc & "00");
|
||||
|
||||
when EXE_RDY =>
|
||||
if MULEN and (r.m.ctrl.wy = '1') then miscout := mey;
|
||||
else miscout := r.m.y; end if;
|
||||
if (NWP > 0) and (r.e.ctrl.inst(18 downto 17) = "11") then
|
||||
wpi := conv_integer(r.e.ctrl.inst(16 downto 15));
|
||||
if r.e.ctrl.inst(14) = '0' then miscout := wpr(wpi).addr & '0' & wpr(wpi).exec;
|
||||
else miscout := wpr(wpi).mask & wpr(wpi).load & wpr(wpi).store; end if;
|
||||
end if;
|
||||
|
||||
-- if MACEN then
|
||||
-- if (r.e.ctrl.inst(18 downto 14) = "10010") then --%ASR18
|
||||
-- if ((r.m.mac = '1') and not MACPIPE) or ((r.x.mac = '1') and MACPIPE) then
|
||||
-- miscout := mulo.result(31 downto 0); -- data forward of asr18
|
||||
-- else miscout := r.w.s.asr18; end if;
|
||||
-- else
|
||||
-- if ((r.m.mac = '1') and not MACPIPE) or ((r.x.mac = '1') and MACPIPE) then
|
||||
-- miscout := mulo.result(63 downto 32); -- data forward Y
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- if (r.e.ctrl.inst(18 downto 17) = "10") and (r.e.ctrl.inst(14) = '1') then --%ASR17
|
||||
-- miscout := asr17_gen(r);
|
||||
-- end if;
|
||||
-- if (r.e.ctrl.inst(18 downto 14) = "10110") then --%ASR22
|
||||
-- miscout(31) := r.w.s.ducnt;
|
||||
-- miscout(30 downto 0) := dbgi.timer(62 downto 32);
|
||||
-- elsif (r.e.ctrl.inst(18 downto 14) = "10111") then --%ASR23
|
||||
-- miscout := dbgi.timer(31 downto 0);
|
||||
-- end if;
|
||||
|
||||
if AWPEN or RFPART then
|
||||
if (r.e.ctrl.inst(18 downto 14) = "10100") then -- %asr20
|
||||
miscout := (others => '0');
|
||||
if AWPEN then
|
||||
miscout(NWINLOG2-1 downto 0) := r.e.awp;
|
||||
end if;
|
||||
if RFPART then
|
||||
miscout(20+NWINLOG2 downto 21) := r.w.s.stwin;
|
||||
miscout(15+NWINLOG2 downto 16) := r.w.s.cwpmax;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
when EXE_SPR =>
|
||||
miscout := get_spr(r, xc_wimmask);
|
||||
when others => null;
|
||||
end case;
|
||||
mout := miscout;
|
||||
|
|
@ -2882,19 +2444,6 @@ end;
|
|||
icc(1) := (op1(31) and op2(31) and not addout(32)) or -- Overflow
|
||||
(addout(32) and (not op1(31)) and (not op2(31)));
|
||||
end if;
|
||||
--if notag = 0 then
|
||||
-- case op is
|
||||
-- when FMT3 =>
|
||||
-- case op3 is
|
||||
-- when TADDCC | TADDCCTV =>
|
||||
-- icc(1) := op1(0) or op1(1) or op2(0) or op2(1) or icc(1);
|
||||
-- when TSUBCC | TSUBCCTV =>
|
||||
-- icc(1) := op1(0) or op1(1) or (not op2(0)) or (not op2(1)) or icc(1);
|
||||
-- when others => null;
|
||||
-- end case;
|
||||
--when others => null;
|
||||
--end case;
|
||||
--end if;
|
||||
|
||||
if aluresult = zero32 then icc(2) := '1'; end if;
|
||||
|
||||
|
|
@ -2904,18 +2453,13 @@ end;
|
|||
when others => aluresult := miscout;
|
||||
end case;
|
||||
|
||||
-- If jump, alu outputs PC to be linked to rd
|
||||
if r.e.jmpl = '1' then aluresult := (r.e.ctrl.pc(31 downto 2) + 1) & "00"; end if;
|
||||
|
||||
|
||||
icc(3) := aluresult(31);
|
||||
--divz := icc(2);
|
||||
if r.e.ctrl.wicc = '1' then
|
||||
-- if (op = FMT3) and (op3 = WRPSR) then icco := logicout(23 downto 20);
|
||||
icco := icc;
|
||||
end if;
|
||||
--elsif r.m.ctrl.wicc = '1' then icco := me_icc;
|
||||
--elsif r.x.ctrl.wicc = '1' then icco := r.x.icc;
|
||||
--else icco := r.w.s.icc; end if;
|
||||
res := aluresult;
|
||||
end;
|
||||
|
||||
|
|
@ -2979,114 +2523,9 @@ end;
|
|||
if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
|
||||
else su := r.w.s.s; end if;
|
||||
if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
|
||||
----------------------------------------------------------------------------
|
||||
|
||||
-- if op = LDST then
|
||||
-- case op3 is
|
||||
-- when LDUB | LDUBA => dci.size := SZBYTE;
|
||||
-- when LDSTUB | LDSTUBA => dci.size := SZBYTE; dci.lock := '1';
|
||||
-- when LDUH | LDUHA => dci.size := SZHALF;
|
||||
-- when LDSB | LDSBA => dci.size := SZBYTE; dci.signed := '1';
|
||||
-- when LDSH | LDSHA => dci.size := SZHALF; dci.signed := '1';
|
||||
-- when LD | LDA | LDF | LDC => dci.size := SZWORD;
|
||||
-- when SWAP | SWAPA => dci.size := SZWORD; dci.lock := '1';
|
||||
-- when CASA => if CASAEN then dci.size := SZWORD; dci.lock := '1'; end if;
|
||||
-- when LDD | LDDA | LDDF | LDDC => dci.size := SZDBL;
|
||||
-- when STB | STBA => dci.size := SZBYTE;
|
||||
-- when STH | STHA => dci.size := SZHALF;
|
||||
-- when ST | STA | STF => dci.size := SZWORD;
|
||||
-- when ISTD | STDA => dci.size := SZDBL;
|
||||
-- when STDF | STDFQ => if FPEN then dci.size := SZDBL; end if;
|
||||
-- when STDC | STDCQ => if CPEN then dci.size := SZDBL; end if;
|
||||
-- when others => dci.size := SZWORD; dci.lock := '0'; dci.signed := '0';
|
||||
-- end case;
|
||||
-- end if;
|
||||
-- link_pc := '0'; jump:= '0'; force_a2 := '0'; load := '0';
|
||||
-- dci.write := '0'; dci.enaddr := '0'; dci.read := not op3(2);
|
||||
|
||||
-- load/store control decoding
|
||||
|
||||
--if (r.e.ctrl.annul or r.e.ctrl.trap) = '0' then
|
||||
-- case op is
|
||||
-- when CALL => link_pc := '1';
|
||||
-- when FMT3 =>
|
||||
-- if r.e.ctrl.trap = '0' then
|
||||
-- case op3 is
|
||||
-- when JMPL => jump := '1'; link_pc := '1';
|
||||
-- when RETT => if REX=0 or r.f.pc(0+2*(1-REX))='0' then jump := '1'; end if;
|
||||
-- when others => null;
|
||||
-- end case;
|
||||
-- end if;
|
||||
-- when LDST =>
|
||||
-- case r.e.ctrl.cnt is
|
||||
-- when "00" =>
|
||||
-- dci.read := op3(3) or not op3(2); -- LD/LDST/SWAP/CASA
|
||||
-- load := op3(3) or not op3(2);
|
||||
-- --dci.enaddr := '1';
|
||||
-- dci.enaddr := (not op3(2)) or op3(2)
|
||||
-- or (op3(3) and op3(2));
|
||||
-- when "01" =>
|
||||
-- force_a2 := not op3(2); -- LDD
|
||||
-- load := not op3(2); dci.enaddr := not op3(2);
|
||||
-- if op3(3 downto 2) = "01" then -- ST/STD
|
||||
-- dci.write := '1';
|
||||
-- end if;
|
||||
-- if (op3(3 downto 2) = "11") and -- LDST/SWAP/CASA
|
||||
-- not (CASAEN and LDDEL=2 and op3(5 downto 4)="11")
|
||||
-- then
|
||||
-- dci.enaddr := '1';
|
||||
-- end if;
|
||||
-- if (CASAEN and LDDEL=2 and op3(5 downto 4)="11") then
|
||||
-- dci.read := '1';
|
||||
-- end if;
|
||||
-- when "10" => -- STD/LDST/SWAP/CASA
|
||||
-- dci.write := '1';
|
||||
-- if (CASAEN and LDDEL=2 and (op3(5 downto 4) = "11")) then -- CASA
|
||||
-- dci.enaddr := '1';
|
||||
-- dci.write := '0';
|
||||
-- end if;
|
||||
-- when others =>
|
||||
-- if (CASAEN and LDDEL=2 and (op3(5 downto 4) = "11")) then -- CASA
|
||||
-- dci.write := '1';
|
||||
-- end if;
|
||||
-- end case;
|
||||
-- if (r.e.ctrl.trap or (v.x.ctrl.trap and not v.x.ctrl.annul)) = '1' then
|
||||
-- dci.enaddr := '0';
|
||||
-- end if;
|
||||
-- if (CASAEN and (op3(5 downto 4) = "11")) then mcasa := '1'; end if;
|
||||
-- when others => null;
|
||||
-- end case;
|
||||
--end if;
|
||||
|
||||
-- if ((r.x.ctrl.rett and not r.x.ctrl.annul) = '1') then su := r.w.s.ps;
|
||||
-- else su := r.w.s.s; end if;
|
||||
-- if su = '1' then dci.asi := "00001011"; else dci.asi := "00001010"; end if;
|
||||
--if (op3(4) = '1') and ((op3(5) = '0') or not CPEN) then
|
||||
-- dci.asi := r.e.ctrl.inst(12 downto 5);
|
||||
-- if r.e.ctrl.inst(12 downto 10) /= "000" then dci.enaddr := '0'; end if;
|
||||
--end if;
|
||||
|
||||
end;
|
||||
|
||||
procedure fpstdata(r : in registers; edata, eres : in word; fpstdata : in std_logic_vector(31 downto 0);
|
||||
edata2, eres2 : out word) is
|
||||
variable op : std_logic_vector(1 downto 0);
|
||||
variable op3 : std_logic_vector(5 downto 0);
|
||||
begin
|
||||
edata2 := edata; eres2 := eres;
|
||||
|
||||
-- RV32I changes
|
||||
|
||||
-- op := r.e.ctrl.inst(31 downto 30); op3 := r.e.ctrl.inst(24 downto 19);
|
||||
-- if FPEN then
|
||||
-- if FPEN and (op = LDST) and ((op3(5 downto 4) & op3(2)) = "101") and (r.e.ctrl.cnt /= "00") then
|
||||
-- edata2 := fpstdata; eres2 := fpstdata;
|
||||
-- end if;
|
||||
-- end if;
|
||||
-- if CASAEN and (r.m.casa = '1') and r.e.ctrl.cnt(1)='1' then
|
||||
-- edata2 := r.e.op1; eres2 := r.e.op1;
|
||||
-- end if;
|
||||
end;
|
||||
|
||||
function ld_align(data : dcdtype; set : std_logic_vector(DSETMSB downto 0);
|
||||
size, laddr : std_logic_vector(1 downto 0); signed : std_ulogic) return word is
|
||||
|
|
@ -3121,6 +2560,7 @@ end;
|
|||
rdata := align_data;
|
||||
end case;
|
||||
|
||||
-- Dummy endian convertion for loaded data
|
||||
outdata(7 downto 0) := rdata(31 downto 24);
|
||||
outdata(15 downto 8) := rdata(23 downto 16);
|
||||
outdata(23 downto 16) := rdata(15 downto 8);
|
||||
|
|
@ -4698,32 +4138,14 @@ begin
|
|||
ex_ymsb := r.e.ymsb; mul_op2 := ex_op2; ex_shcnt := r.e.shcnt;
|
||||
v.e.cwp := r.a.cwp; ex_sari := r.e.sari;
|
||||
v.m.su := r.e.su;
|
||||
-- May remove this
|
||||
if MULTYPE = 3 then v.m.mul := r.e.mul; else v.m.mul := '0'; end if;
|
||||
if lddel = 1 then
|
||||
if r.e.ldbp1 = '1' then
|
||||
ex_op1 := r.x.data(0);
|
||||
ex_sari := r.x.data(0)(31) and r.e.ctrl.inst(19) and r.e.ctrl.inst(20);
|
||||
end if;
|
||||
if r.e.ldbp2 = '1' then
|
||||
ex_op2 := r.x.data(0); ex_ymsb := r.x.data(0)(0);
|
||||
mul_op2 := ex_op2; ex_shcnt := r.x.data(0)(4 downto 0);
|
||||
if r.e.invop2 = '1' then
|
||||
ex_op2 := not ex_op2; ex_shcnt := not ex_shcnt;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
---
|
||||
|
||||
-- Adder
|
||||
ex_add_res := (ex_op1 & '1') + (ex_op2 & r.e.alucin);
|
||||
|
||||
if ex_add_res(2 downto 1) = "00" then v.m.nalign := '0';
|
||||
else v.m.nalign := '1'; end if;
|
||||
-- if REX=1 then
|
||||
-- if ex_add_res(2 downto 1) /= "10" then v.m.rexnalign := '0';
|
||||
-- else v.m.rexnalign := '1'; end if;
|
||||
-- end if;
|
||||
|
||||
-- Generates data cache control signals
|
||||
dcache_gen(r, v, ex_dci, ex_link_pc, ex_jump, ex_force_a2, ex_load, v.m.casa);
|
||||
|
||||
-- RV32I change
|
||||
|
|
@ -4733,37 +4155,29 @@ begin
|
|||
ex_jump_address := ex_add_res(32 downto PCLOW+1) + r.e.ctrl.pc(31 downto PCLOW);
|
||||
end if;
|
||||
|
||||
-- Logical insts
|
||||
logic_op(r, ex_op1, ex_op2, v.x.y, ex_ymsb, ex_logic_res, v.m.y);
|
||||
|
||||
-- Shifts
|
||||
ex_shift_res := shift(r, ex_op1, ex_op2, ex_shcnt, ex_sari);
|
||||
|
||||
-- Load/Store, jump, branch uses this
|
||||
misc_op(r, wpr, ex_op1, ex_op2, xc_df_result, v.x.y, xc_wimmask, ex_misc_res, ex_edata);
|
||||
ex_add_res(3):= ex_add_res(3) or ex_force_a2;
|
||||
if CASAEN and LDDEL=2 and (r.m.casa='1' and r.e.ctrl.cnt="11") then
|
||||
ex_add_res(32 downto 1) := r.e.op2;
|
||||
end if;
|
||||
|
||||
-- Select which operation ALU is supposed to execute
|
||||
alu_select(r, ex_add_res, ex_op1, ex_op2, ex_shift_res, ex_logic_res,
|
||||
ex_misc_res, ex_result, me_icc, v.m.icc, v.m.divz, v.m.casaz);
|
||||
|
||||
-- Generates debug unit output
|
||||
dbg_cache(holdn, dbgi, r, dsur, ex_result, ex_dci, ex_result2, v.m.dci);
|
||||
fpstdata(r, ex_edata, ex_result2, fpo.data, ex_edata2, ex_result3);
|
||||
|
||||
v.m.result := ex_result3;
|
||||
cwp_ex(r, v.m.wcwp, v.m.wawp);
|
||||
|
||||
-- if CASAEN and ( (LDDEL=1 and (r.m.casa='1' and r.e.ctrl.cnt="10")) or
|
||||
-- (LDDEL=2 and (r.m.casa='1' and r.e.ctrl.cnt="11")))
|
||||
-- and v.m.casaz='0' then
|
||||
-- me_nullify2 := '1';
|
||||
-- end if;
|
||||
-- dci.nullify <= me_nullify2;
|
||||
dci.nullify <= '0';
|
||||
|
||||
ex_mulop1 := (ex_op1(31) and r.e.ctrl.inst(19)) & ex_op1;
|
||||
ex_mulop2 := (mul_op2(31) and r.e.ctrl.inst(19)) & mul_op2;
|
||||
|
||||
if is_fpga(fabtech) = 0 and (r.e.mul = '0') then -- power-save for mul
|
||||
-- if (r.e.mul = '0') then
|
||||
ex_mulop1 := (others => '0'); ex_mulop2 := (others => '0');
|
||||
end if;
|
||||
|
||||
|
||||
-- Updates control registers for next pipeline stage
|
||||
v.m.ctrl.annul := v.m.ctrl.annul or v.x.annul_all;
|
||||
v.m.ctrl.wicc := r.e.ctrl.wicc and not v.x.annul_all;
|
||||
v.m.mac := r.e.mac;
|
||||
|
|
@ -4780,6 +4194,7 @@ begin
|
|||
-- REGFILE STAGE
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
-- May change this for trap/exceptions support
|
||||
--Resource Sharing between hardware breakpoint detection
|
||||
--and instruction trace buffer filter
|
||||
pccompare(r,wpr,pccomp);
|
||||
|
|
@ -4833,6 +4248,7 @@ begin
|
|||
de_rexbubble := '0'; de_rexbaddr1:='0'; de_reximmexp:='0'; de_reximmval:=(others => '0');
|
||||
de_rexmaskpv := '0'; de_rexillinst:='0'; de_rexnostep:='0';
|
||||
|
||||
-- Dummy endian change for fetched instruction
|
||||
--de_inst := de_inst1;
|
||||
de_inst(7 downto 0) := de_inst1(31 downto 24);
|
||||
de_inst(15 downto 8) := de_inst1(23 downto 16);
|
||||
|
|
@ -4870,10 +4286,6 @@ begin
|
|||
rd_gen(r, de_inst, v.a.ctrl.wreg, v.a.ctrl.ld, de_rd, de_rexen);
|
||||
regaddr(de_cwp, de_rd, r.d.stwin, r.d.cwpmax, v.a.ctrl.rd);
|
||||
|
||||
-- No FP unit
|
||||
-- fpbranch(de_inst, fpo.cc, de_fbranch);
|
||||
-- fpbranch(de_inst, cpo.cc, de_cbranch);
|
||||
|
||||
-- Get immediate
|
||||
v.a.imm := imm_data(r, de_inst, de_reximmexp, de_reximmval);
|
||||
de_iperr := '0';
|
||||
|
|
@ -5043,11 +4455,6 @@ begin
|
|||
|
||||
end if;
|
||||
|
||||
-- For pipelined REX implementation
|
||||
--if REX/=0 and REXPIPE then
|
||||
-- rex_pl_fetch(v.d,r.d,holdn,
|
||||
-- v.d.rexpl);
|
||||
--end if;
|
||||
-----------------------------------------------------------------------
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
|
|
@ -5108,39 +4515,6 @@ begin
|
|||
dbgo.ducnt <= r.w.s.ducnt;
|
||||
|
||||
vfpi := fpc_in_none;
|
||||
--if FPEN then
|
||||
-- if (r.x.rstate = dsu2) then vfpi.flush := '1'; else vfpi.flush := v.x.annul_all and holdn; end if;
|
||||
-- vfpi.exack := xc_fpexack; vfpi.a_rs1 := r.a.rs1; vfpi.d.inst := de_inst;
|
||||
-- vfpi.d.cnt := r.d.cnt;
|
||||
-- vfpi.d.annul := v.x.annul_all or de_bpannul or r.d.annul or de_fins_hold or (ico.bpmiss and not r.d.pcheld)
|
||||
-- ;
|
||||
-- if REX=1 then vfpi.d.annul := vfpi.d.annul or de_rexbubble; end if;
|
||||
-- vfpi.d.trap := r.d.mexc;
|
||||
-- vfpi.d.pc(1 downto 0) := (others => '0'); vfpi.d.pc(31 downto PCLOW) := r.d.pc(31 downto PCLOW);
|
||||
-- vfpi.d.pv := r.d.pv;
|
||||
-- vfpi.a.pc(1 downto 0) := (others => '0'); vfpi.a.pc(31 downto PCLOW) := r.a.ctrl.pc(31 downto PCLOW);
|
||||
-- vfpi.a.inst := r.a.ctrl.inst; vfpi.a.cnt := r.a.ctrl.cnt; vfpi.a.trap := r.a.ctrl.trap;
|
||||
-- vfpi.a.annul := r.a.ctrl.annul or (ex_bpmiss and r.e.ctrl.inst(29))
|
||||
-- ;
|
||||
-- vfpi.a.pv := r.a.ctrl.pv;
|
||||
-- vfpi.e.pc(1 downto 0) := (others => '0'); vfpi.e.pc(31 downto PCLOW) := r.e.ctrl.pc(31 downto PCLOW);
|
||||
-- vfpi.e.inst := r.e.ctrl.inst; vfpi.e.cnt := r.e.ctrl.cnt; vfpi.e.trap := r.e.ctrl.trap; vfpi.e.annul := r.e.ctrl.annul;
|
||||
-- vfpi.e.pv := r.e.ctrl.pv;
|
||||
-- vfpi.m.pc(1 downto 0) := (others => '0'); vfpi.m.pc(31 downto PCLOW) := r.m.ctrl.pc(31 downto PCLOW);
|
||||
-- vfpi.m.inst := r.m.ctrl.inst; vfpi.m.cnt := r.m.ctrl.cnt; vfpi.m.trap := r.m.ctrl.trap; vfpi.m.annul := r.m.ctrl.annul;
|
||||
-- vfpi.m.pv := r.m.ctrl.pv;
|
||||
-- vfpi.x.pc(1 downto 0) := (others => '0'); vfpi.x.pc(31 downto PCLOW) := r.x.ctrl.pc(31 downto PCLOW);
|
||||
-- vfpi.x.inst := r.x.ctrl.inst; vfpi.x.cnt := r.x.ctrl.cnt; vfpi.x.trap := xc_trap;
|
||||
-- vfpi.x.annul := r.x.ctrl.annul; vfpi.x.pv := r.x.ctrl.pv;
|
||||
-- if (lddel = 2) then vfpi.lddata := r.x.data(conv_integer(r.x.set)); else vfpi.lddata := r.x.data(0); end if;
|
||||
-- if (r.x.rstate = dsu2)
|
||||
-- then vfpi.dbg.enable := dbgi.denable;
|
||||
-- else vfpi.dbg.enable := '0'; end if;
|
||||
-- vfpi.dbg.write := fpcdbgwr;
|
||||
-- vfpi.dbg.fsr := dbgi.daddr(22); -- IU reg access
|
||||
-- vfpi.dbg.addr := dbgi.daddr(6 downto 2);
|
||||
-- vfpi.dbg.data := dbgi.ddata;
|
||||
-- end if;
|
||||
fpi <= vfpi;
|
||||
cpi <= vfpi; -- dummy, just to kill some warnings ...
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue