First modifications for special registers

lib/gaisler/leon3v3/iu3.vhd

@@ -443,6 +443,23 @@ architecture rtl of iu3 is
     stwin  : cwptype;                   -- starting window
     cwpmax : cwptype;                   -- max cwp value
     ducnt  : std_ulogic;
+
+    -- RISC-V CSRs used by GNU/Linux    -- Encoding
+    status   : word                     -- 0
+    epc      : pctype;                  -- 1
+    badvaddr : word;                    -- 2
+    evec     : word := x"40000100";     -- 3
+    count    : word;                    -- 4
+    compare  : word;                    -- 5
+    cause    : word;                    -- 6
+    ptbr     : word;                    -- 7
+    k0       : word;                    -- 12
+    k1       : word;                    -- 13
+    tosim    : word;                    -- 26
+    fromsim  : word;                    -- 27
+    tohost   : word;                    -- 30
+    fromhost : word;                    -- 31
+
   end record;
 
   type write_reg_type is record
@@ -1581,6 +1598,8 @@ begin
           when  R_LUI | R_AUIPC | R_JAL | R_JALR | R_BRANCH | R_LD | R_ST | R_IMM
             | R_NOIMM =>
                 illegal_inst := '0';
+
+          when
           when others =>
                 illegal_inst := '1';
         end case;

riscv/log

@@ -0,0 +1,46 @@
+
+reonv_crt0.o:     file format elf32-littleriscv
+
+
+Disassembly of section .text:
+
+00000000 <__reonv_startup>:
+   0:	00000093          	li	ra,0
+   4:	00000113          	li	sp,0
+   8:	00000193          	li	gp,0
+   c:	00000213          	li	tp,0
+  10:	00000293          	li	t0,0
+  14:	00000313          	li	t1,0
+  18:	00000393          	li	t2,0
+  1c:	00000413          	li	s0,0
+  20:	00000493          	li	s1,0
+  24:	00000513          	li	a0,0
+  28:	00000593          	li	a1,0
+  2c:	00000613          	li	a2,0
+  30:	00000693          	li	a3,0
+  34:	00000713          	li	a4,0
+  38:	00000793          	li	a5,0
+  3c:	00000813          	li	a6,0
+  40:	00000893          	li	a7,0
+  44:	00000913          	li	s2,0
+  48:	00000993          	li	s3,0
+  4c:	00000a13          	li	s4,0
+  50:	00000a93          	li	s5,0
+  54:	00000b13          	li	s6,0
+  58:	00000b93          	li	s7,0
+  5c:	00000c13          	li	s8,0
+  60:	00000c93          	li	s9,0
+  64:	00000d13          	li	s10,0
+  68:	00000d93          	li	s11,0
+  6c:	00000e13          	li	t3,0
+  70:	00000e93          	li	t4,0
+  74:	00000f13          	li	t5,0
+  78:	00000f93          	li	t6,0
+  7c:	42000137          	lui	sp,0x42000
+  80:	00000097          	auipc	ra,0x0
+  84:	000080e7          	jalr	ra
+  88:	004000ef          	jal	ra,8c <__exit>
+
+0000008c <__exit>:
+  8c:	00100073          	ebreak
+	...

riscv/reonv_crt0.S

@@ -1,12 +1,18 @@
+
+#define EX_STACK_SIZE 128
+
 .file "reonv_crt0.S"
 .extern _start
 .extern main
 .globl __reonv_startup
 .type "__reonv_startup",@function
 
-# Build minimal crt0 in future
-__reonv_startup:
-	# Clean registers and set stack (maybe will change this to boot code)
+/* Build minimal crt0 */
+
+reonv_reset_handler:
+	/* Have to configure CSRs in future */
+
+	/* Clean registers and set stack */
 	addi	x1,x0,0
 	addi	x2,x0,0
 	addi	x3,x0,0
@@ -40,16 +46,33 @@ __reonv_startup:
 	addi	x31,x0,0
 
 	li	sp,0x42000000
+
+	/* Call initialzation procedures */
+
+	/* Call main (or kernel in future) */
 	call 	main
 	jal 	__exit
 
-# Exit routine
+/* Exit routine */
 __exit:
 	ebreak
 
+__save_regs:
+
+
+__load_regs:
+
+
+__ex_handler:
+	addi	sp,sp,-EX_STACK_SIZE
+
+
+
+
+.org 0x100
 # Interruptions vector
 __interruption_vector:
-
+	ebreak