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@ -17,7 +17,7 @@ make main.out
---
## Synthetizing and loading design to FPGA
To synthetize ReonV you must change to your board design directory, in this example it is `designs/leon3-digilent-nexys4ddr`. There is a README in each design directory, follow the instructions there to synthetize and load the design to FPGA. In this example, they are:
To synthesize ReonV you must change to your board design directory, in this example it is `designs/leon3-digilent-nexys4ddr`. There is a README in each design directory, follow the instructions there to synthesize and load the design to FPGA. In this example, they are:
```
make sim
make vivado