github-mirrors/ReonV
1
0
Fork 0
mirror of https://github.com/lcbcFoo/ReonV.git synced 2025-04-18 18:44:43 -04:00
Code Issues Projects Releases Packages Wiki Activity Actions

Update README.md

Browse source
This commit is contained in:
lcbcFoo 2018-03-13 15:46:56 -03:00 • committed by GitHub
parent 5b22387862
commit a4325d60ab
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
riscv/README.md
View file

@ -5,7 +5,7 @@ changing a few commands to the ones your board requires.
---
## Overview
* ReonV currentily implements RV32I without privilegied instructions, so it is important to use a compiler to this ISA (follow instructions on the main README).
* ReonV currently implements RV32I without privileged instructions, so it is important to use a compiler to this ISA (follow instructions on the main README).
* We will use GRMON2 to load, run and debug the program, since the processor DSU was not changed and it communicates with GRMON. However, GRMON2 was not designed for RISC-V and we have to take some workarounds to run a RISC-V program using it (more information on issue [GRMON2 and RISCV](https://github.com/lcbcFoo/ReonV/issues/5))
* The design directory for this board is `designs/leon3-digilent-nexys4ddr`. If you are running on other board, you must use its own design directory.